shifter.vhd

-------------------------------------------------------------------------------
-- Project  ELE8304 : Circuits intégrés à très grande échelle
-------------------------------------------------------------------------------
-- File     shifter.vhd
-- Authors  Titouan Luard <luardtitouan@gmail.com> 
--          Yann Roberge <yann.roberge@polymtl.ca> 
-- Lab      GRM - Polytechnique Montreal
-- Date     2021-10-29
-------------------------------------------------------------------------------
-- Brief    Single-bit half-adder with carry out
------------------------------------------------------------------------
-------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;


library work;
use work.riscv_pkg.all;

entity shifter is
  port (
    i_shamt     : in  std_logic_vector(4 downto 0); -- nombre de bits décalés
    i_src1      : in  std_logic_vector(XLEN-1 downto 0); -- nombre décalé
    i_arith     : in  std_logic; -- 0: décalage logique (bourre des 0) ; 1
    i_opcode    : in  std_logic_vector(2 downto 0);
    
    o_sh  : out std_logic_vector(XLEN-1 downto 0) );

end entity shifter;

--SRL 000
--SRA 001
--SLL 010
architecture beh of shifter is
signal temp : std_logic_vector(XLEN-1 downto 0);
begin

shift: 
process (all) is
begin
  case i_opcode is
    when "000" =>
      if i_arith='0' then
     --decalage a droite logique 
         o_sh <= i_src1 srl to_integer(unsigned(i_shamt));
      else
        if i_src1(XLEN-1)='0' then
          o_sh <= i_src1 srl to_integer(unsigned(i_shamt));
        else
          temp <= i_src1 srl to_integer(unsigned(i_shamt));
          o_sh <= not temp(temp'length - 1 downto temp'length - to_integer(unsigned(i_shamt))) & i_src1(temp'length - 1 - to_integer(unsigned(i_shamt)) downto 0);
        end if;
      end if;
    when "001" =>
    --decalage a droite arithmetique
      o_sh <= i_src1 sll to_integer(unsigned(i_shamt));
       

    when others=> o_sh<= i_src1;
  end case;
end process shift;


end architecture beh;