MàJ du shifteur non testée

sources/shifter.vhd

@@ -8,80 +8,59 @@
 -- Date     2021-10-29
 -------------------------------------------------------------------------------
 -- Brief    Single-bit half-adder with carry out
--------------------------------------------------------------------------------
+------------------------------------------------------------------------
+-------
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 use ieee.math_real.all;
 
+
 library work;
 use work.riscv_pkg.all;
 
 entity shifter is
   port (
     i_shamt     : in  std_logic_vector(4 downto 0); -- nombre de bits décalés
-    i_src1      : in  std_logic_vector(4 downto 0); -- nombre décalé
+    i_src1      : in  std_logic_vector(XLEN-1 downto 0); -- nombre décalé
     i_arith     : in  std_logic; -- 0: décalage logique (bourre des 0) ; 1
-    i_opcode    : in  std_logic_vector(6 downto 0);
-    i_funct3    : in  std_logic_vector(2 downto 0);
+    i_opcode    : in  std_logic_vector(2 downto 0);
     
-    o_sh  : out std_logic_vector  );
+    o_sh  : out std_logic_vector(XLEN-1 downto 0) );
 
 end entity shifter;
 
---Si i_opcode="0110011" pas immediat, i_opcode="0010011" immediat.
-
+--SRL 000
+--SRA 001
+--SLL 010
 architecture beh of shifter is
-
-signal temp : std_logic_vector(4 downto 0);
-
+signal temp : std_logic_vector(XLEN-1 downto 0);
 begin
 
-decode:
+shift: 
 process (all) is
 begin
   case i_opcode is
-    when "011011" =>
-
-     --decalage a gauche logique 
-       if i_funct3= "001" then
-        o_sh <= i_src1 sll to_integer(unsigned(i_shamt));
-
-    --decalage a droite logique 
-      elsif i_funct3= "101" and i_arith='0'then 
-        o_sh <= i_src1 srl to_integer(unsigned(i_shamt));
-
-    --decalage a droite arithmetique 
-      elsif i_funct3= "101" and i_arith='1'then 
-        if i_src1(4)='0' then
+    when "000" =>
+      if i_arith='0' then
+     --decalage a droite logique 
+         o_sh <= i_src1 srl to_integer(unsigned(i_shamt));
+      else
+        if i_src1(2)='0' then 
           o_sh <= i_src1 srl to_integer(unsigned(i_shamt));
-          elsif i_src1(4)='1' then
-          temp <=i_src1 srl to_integer(unsigned(i_shamt));
-          o_sh <= not temp(4 downto to_integer(unsigned(i_shamt))) &   i_src1(to_integer(unsigned(i_shamt)) downto 0);
+        else
+          temp  <= i_src1 srl to_integer(unsigned(i_shamt));
+          o_sh <= not temp(temp'length - 1 downto temp'length -1 - to_integer(unsigned(i_shamt))) & i_src1(temp'length - 2 - to_integer(unsigned(i_shamt)) downto 0);
         end if;
-    end if;
-    when "001011"=>
-
-     --decalage a gauche logique 
-       if i_funct3= "001" then
-        o_sh <= i_src1 sll to_integer(unsigned(i_shamt));
-
-    --decalage a droite logique 
-      elsif i_funct3= "101" and i_arith='0'then 
-        o_sh <= i_src1 srl to_integer(unsigned(i_shamt));
-
-    --decalage a droite arithmetique 
-      elsif i_funct3= "101" and i_arith='1'then 
-        if i_src1(4)='0' then
-          o_sh <= i_src1 srl to_integer(unsigned(i_shamt));
-          elsif i_src1(4)='1' then
-          temp <=i_src1 srl to_integer(unsigned(i_shamt));
-          o_sh <= not temp(4 downto to_integer(unsigned(i_shamt))) &   i_src1(to_integer(unsigned(i_shamt)) downto 0);
       end if;
-    end if;
+    when "001" =>
+    --decalage a droite arithmetique
+      o_sh <= i_src1 sll to_integer(unsigned(i_shamt));
+       
+
     when others=> o_sh<= i_src1;
   end case;
-end process decode;
+end process shift;
 
 
 end architecture beh;

sources/shifter_tb.vhd

@@ -20,101 +20,98 @@ use work.riscv_pkg.all;
 entity shifter_tb is
 end shifter_tb;
 
-architecture tb of half_adder_tb is
+architecture tb of shifter_tb is
 
-  signal src    : std_logic;
-  signal opcode : std_logic;
-  signal shamt  : std_logic;
-  signal funct3 : std_logic;
-  signal out    : std_logic;
+  signal src1    : std_logic_vector(3 downto 0);
+  signal arith  : std_logic;
+  signal opcode : std_logic_vector(2 downto 0);
+  signal shamt  : std_logic_vector(6 downto 0);
+  signal output : std_logic_vector(3 downto 0);
 
   constant PERIOD   : time := 10 ns;
 
 begin
 
   -- DUT
-  dut: entity work.half_adder
+  dut: entity work.shifter
     port map (
-      i_src1  => src;
-      i_opcode => b;
-      i_arith => arith;
-      i_shamt => shamt;
-      i_funct3 =>funct3;
-      o_sh => out;
-    );
+      i_src1  => src1,
+      i_opcode => opcode,
+      i_arith => arith,
+      i_shamt => shamt,
+      o_sh => output);
+      
   -- Main TB process
   p_main : process
   begin
     report "BEGIN SIMULATION";
     report "SHIFT";
-    -- decalage logique à gauche
-    src1 <= '0100';
-    opcode <= '0110011';
-    funct3 <= '001'
-    shamt<= '1'
+    -- decalage logique à droite
+    src1 <= "0100";
+    opcode <= "000";
+    shamt<= '1';
     wait for PERIOD;
 
-    assert out = '0101'
-      report "Shift error" severity error;
+    assert out = "0010"
+      report "Shift droite logique error" severity error;
     wait for PERIOD;
-    -- decalage logique à droite
-    src1 <= '1010';
-    opcode <= '0110011';
-    funct3 <= '101'
-    arith <= '0'
+    -- decalage arithmetique à droite
+    src1 <= "1010";
+    opcode <= "001";
+    arith <= '1'
     shamt<= '1'
     
     wait for PERIOD;
 
-    assert out = '0101'
+    assert out = "0101"
       report "Shift error" severity error;
     wait for PERIOD;
     -- decalage arithmetique à droite
-    src1 <= '1010';
-    opcode <= '0110011';
-    funct3 <= '101'
+    src1 <= "1010";
+    opcode <= "0110011";
+    funct3 <= "101"
     arith <= '1'
     shamt<= '1'
     
     wait for PERIOD;
 
-    assert out = '1101'
+    assert out = "1101"
       report "Shift error" severity error;
     wait for PERIOD;
 
      report "SHIFT IMMEDIATE";
     -- decalage logique à gauche
-    src1 <= '0100';
-    opcode <= '0010011';
-    funct3 <= '001'
+    src1 <= "0100";
+    opcode <= "0010011";
+    funct3 <= "001"
     shamt<= '1'
     wait for PERIOD;
 
-    assert out = '0101'
+    assert out = "0101"
       report "Shift error" severity error;
     wait for PERIOD;
     -- decalage logique à droite
-    src1 <= '1010';
-    opcode <= '0010011';
-    funct3 <= '101'
+    src1 <="1010";
+    opcode <= "0010011";
+    funct3 <= "101"
     arith <= '0'
     shamt<= '1'
     
     wait for PERIOD;
 
-    assert out = '0101'
+    assert out = "0101"
       report "Shift error" severity error;
     wait for PERIOD;
     -- decalage arithmetique à droite
-    src1 <= '1010';
-    opcode <= '0010011';
-    funct3 <= '101'
+    src1 <= "1010";
+    opcode <= "0010011";
+    funct3 <= "101"
     arith <= '1'
     shamt<= '1'
     
     wait for PERIOD;
 
-    assert out = '1101'
+    assert out = "1101"
       report "Shift error" severity error;
     wait for PERIOD;