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Commit 20388e87 authored by 8304_9's avatar 8304_9
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Version initiale des shifters

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-------------------------------------------------------------------------------
-- Project ELE8304 : Circuits intégrés à très grande échelle
-------------------------------------------------------------------------------
-- File shifter.vhd
-- Authors Titouan Luard <luardtitouan@gmail.com>
-- Yann Roberge <yann.roberge@polymtl.ca>
-- Lab GRM - Polytechnique Montreal
-- Date 2021-10-29
-------------------------------------------------------------------------------
-- Brief Single-bit half-adder with carry out
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.riscv_pkg.all;
entity shifter is
port (
i_shamt : in std_logic_vector(4 downto 0); -- nombre de bits décalés
i_src1 : in std_logic_vector(4 downto 0); -- nombre décalé
i_arith : in std_logic; -- 0: décalage logique (bourre des 0) ; 1
i_opcode : in std_logic_vector(6 downto 0);
i_funct3 : in std_logic_vector(2 downto 0);
o_sh : out std_logic_vector );
end entity shifter;
--Si i_opcode="0110011" pas immediat, i_opcode="0010011" immediat.
architecture beh of shifter is
signal temp : std_logic_vector(4 downto 0);
begin
decode:
process (all) is
begin
case i_opcode is
when "011011" =>
--decalage a gauche logique
if i_funct3= "001" then
o_sh <= i_src1 sll to_integer(unsigned(i_shamt));
--decalage a droite logique
elsif i_funct3= "101" and i_arith='0'then
o_sh <= i_src1 srl to_integer(unsigned(i_shamt));
--decalage a droite arithmetique
elsif i_funct3= "101" and i_arith='1'then
if i_src1(4)='0' then
o_sh <= i_src1 srl to_integer(unsigned(i_shamt));
elsif i_src1(4)='1' then
temp <=i_src1 srl to_integer(unsigned(i_shamt));
o_sh <= not temp(4 downto to_integer(unsigned(i_shamt))) & i_src1(to_integer(unsigned(i_shamt)) downto 0);
end if;
end if;
when "001011"=>
--decalage a gauche logique
if i_funct3= "001" then
o_sh <= i_src1 sll to_integer(unsigned(i_shamt));
--decalage a droite logique
elsif i_funct3= "101" and i_arith='0'then
o_sh <= i_src1 srl to_integer(unsigned(i_shamt));
--decalage a droite arithmetique
elsif i_funct3= "101" and i_arith='1'then
if i_src1(4)='0' then
o_sh <= i_src1 srl to_integer(unsigned(i_shamt));
elsif i_src1(4)='1' then
temp <=i_src1 srl to_integer(unsigned(i_shamt));
o_sh <= not temp(4 downto to_integer(unsigned(i_shamt))) & i_src1(to_integer(unsigned(i_shamt)) downto 0);
end if;
end if;
when others=> o_sh<= i_src1;
end case;
end process decode;
end architecture beh;
-------------------------------------------------------------------------------
-- Project ELE8304 : Circuits intégrés à très grande échelle
-------------------------------------------------------------------------------
-- File shifter_tb.vhd
-- Authors Titouan Luard <luardtitouan@gmail.com>
-- Yann Roberge <yann.roberge@polymtl.ca>
-- Lab GRM - Polytechnique Montreal
-- Date 2021-10-29
-------------------------------------------------------------------------------
-- Brief Single-bit half-adder with carry out
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.riscv_pkg.all;
entity shifter_tb is
end shifter_tb;
architecture tb of half_adder_tb is
signal src : std_logic;
signal opcode : std_logic;
signal shamt : std_logic;
signal funct3 : std_logic;
signal out : std_logic;
constant PERIOD : time := 10 ns;
begin
-- DUT
dut: entity work.half_adder
port map (
i_src1 => src;
i_opcode => b;
i_arith => arith;
i_shamt => shamt;
i_funct3 =>funct3;
o_sh => out;
);
-- Main TB process
p_main : process
begin
report "BEGIN SIMULATION";
report "SHIFT";
-- decalage logique à gauche
src1 <= '0100';
opcode <= '0110011';
funct3 <= '001'
shamt<= '1'
wait for PERIOD;
assert out = '0101'
report "Shift error" severity error;
wait for PERIOD;
-- decalage logique à droite
src1 <= '1010';
opcode <= '0110011';
funct3 <= '101'
arith <= '0'
shamt<= '1'
wait for PERIOD;
assert out = '0101'
report "Shift error" severity error;
wait for PERIOD;
-- decalage arithmetique à droite
src1 <= '1010';
opcode <= '0110011';
funct3 <= '101'
arith <= '1'
shamt<= '1'
wait for PERIOD;
assert out = '1101'
report "Shift error" severity error;
wait for PERIOD;
report "SHIFT IMMEDIATE";
-- decalage logique à gauche
src1 <= '0100';
opcode <= '0010011';
funct3 <= '001'
shamt<= '1'
wait for PERIOD;
assert out = '0101'
report "Shift error" severity error;
wait for PERIOD;
-- decalage logique à droite
src1 <= '1010';
opcode <= '0010011';
funct3 <= '101'
arith <= '0'
shamt<= '1'
wait for PERIOD;
assert out = '0101'
report "Shift error" severity error;
wait for PERIOD;
-- decalage arithmetique à droite
src1 <= '1010';
opcode <= '0010011';
funct3 <= '101'
arith <= '1'
shamt<= '1'
wait for PERIOD;
assert out = '1101'
report "Shift error" severity error;
wait for PERIOD;
end process p_main;
end architecture tb;
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