Corrections au shifter et instanciation dans l'ALU

sources/riscv_alu.vhd

@@ -31,9 +31,6 @@ end entity riscv_alu;
 
 
 architecture beh of riscv_alu is
-  -- Signaux utilisés par le shifteur
-  --type shifted_t is array (natural ) of std_logic_vector(XLEN-1 downto 0);
-  --signal shifted_by : shifted_t(SHAMT_WIDTH'length - 1 downto 0);
 
   -- Signaux en entrée du multiplexeur
   signal shifter_result : std_logic_vector(XLEN-1 downto 0);
@@ -56,8 +53,13 @@ begin
       o_sum  => adder_result);
 
   -- Barrel Shifter
-  -- TODO: 
-  shifter_result <= (others => '1');
+  shifter: entity work.shifter
+    port map (
+      i_shamt  => i_shamt,
+      i_src1   => i_src1,
+      i_arith  => i_arith,
+      i_opcode => i_opcode,
+      o_sh     => shifter_result);
   
   -- Unité logique
   and_result <= i_src1 and i_src2;

sources/riscv_alu_tb.vhd

@@ -65,10 +65,8 @@ architecture tb of riscv_alu_tb is
       wait for period;
   end procedure test_vector;
 
-
   constant PERIOD : time := 10 ns;
 
-  --constant SHAMT_TESTED := std_logic_vector(SHAMT_WIDTH-1 downto 0) := 
 begin
 
   -- Instanciation du DUT
@@ -107,7 +105,7 @@ begin
       src2   => src2,
       res    => res,
 
-      expected_result => (XLEN-1 downto XLEN-2 => "00", others => '1'),
+      expected_result => (1 downto 0 => "00", others => '1'),
       period => PERIOD
     );
 
@@ -129,7 +127,7 @@ begin
       src2   => src2,
       res    => res,
 
-      expected_result => (1 downto 0 => "00", others => '1'),
+      expected_result => (XLEN-1 downto XLEN-2 => "00", others => '1'),
       period => PERIOD
     );
 

sources/shifter.vhd

@@ -46,11 +46,11 @@ begin
      --decalage a droite logique 
          o_sh <= i_src1 srl to_integer(unsigned(i_shamt));
       else
-        if i_src1(2)='0' then 
+        if i_src1(XLEN-1)='0' then
           o_sh <= i_src1 srl to_integer(unsigned(i_shamt));
         else
-          temp  <= i_src1 srl to_integer(unsigned(i_shamt));
-          o_sh <= not temp(temp'length - 1 downto temp'length -1 - to_integer(unsigned(i_shamt))) & i_src1(temp'length - 2 - to_integer(unsigned(i_shamt)) downto 0);
+          temp <= i_src1 srl to_integer(unsigned(i_shamt));
+          o_sh <= not temp(temp'length - 1 downto temp'length - to_integer(unsigned(i_shamt))) & i_src1(temp'length - 1 - to_integer(unsigned(i_shamt)) downto 0);
         end if;
       end if;
     when "001" =>