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Commit 9a73508e authored by Yann Roberge's avatar Yann Roberge
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Avancé le TB du module decode

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sources/riscv_decode.vhd
+ 1
− 1
View file @ 9a73508e
......@@ -28,7 +28,7 @@ entity riscv_decode is
-- Entrées provenant de l'étage WRITE-BACK
i_wr_addr : in std_logic_vector(REG_WIDTH-1 downto 0);
i_wr_data : in std_logic_vector(REG_WIDTH-1 downto 0);
i_wr_data : in std_logic_vector(XLEN-1 downto 0);
i_we : in std_logic;
-- Entrée provenant de l'étage EXECUTE
......
sources/riscv_decode_tb.vhd
+ 83
− 37
View file @ 9a73508e
......@@ -27,7 +27,7 @@ architecture tb of riscv_decode_tb is
signal instruction : std_logic_vector(XLEN-1 downto 0);
signal pc_i : std_logic_vector(XLEN-1 downto 0);
signal wr_addr : std_logic_vector(REG_WIDTH-1 downto 0);
signal wr_data : std_logic_vector(REG_WIDTH-1 downto 0);
signal wr_data : std_logic_vector(XLEN-1 downto 0);
signal we : std_logic;
signal flush : std_logic;
signal rstn : std_logic;
......@@ -45,21 +45,21 @@ architecture tb of riscv_decode_tb is
-- Write to a register, no checking of what's coming out
-- TODO: Adapter
procedure write_reg (
signal addr_w : out std_logic_vector(REG_WIDTH-1 downto 0);
signal data_w : out std_logic_vector(XLEN-1 downto 0);
signal wr_addr : out std_logic_vector(REG_WIDTH-1 downto 0);
signal wr_data : out std_logic_vector(XLEN-1 downto 0);
signal we : out std_logic;
constant test_addr_w : in std_logic_vector(REG_WIDTH-1 downto 0);
constant test_data_w : in std_logic_vector(XLEN-1 downto 0);
constant test_wr_addr : in std_logic_vector(REG_WIDTH-1 downto 0);
constant test_wr_data : in std_logic_vector(XLEN-1 downto 0);
constant period : in time) is
begin
addr_w <= test_addr_w;
data_w <= test_data_w;
wr_addr <= test_wr_addr;
wr_data <= test_wr_data;
we <= '1';
wait for period;
report "Wrote " & to_string(data_w) & " to reg " & to_string(addr_w);
report "Wrote " & to_string(wr_data) & " to reg " & to_string(wr_addr);
end procedure write_reg;
......@@ -69,7 +69,7 @@ architecture tb of riscv_decode_tb is
signal instruction : out std_logic_vector(XLEN-1 downto 0);
signal pc_i : out std_logic_vector(XLEN-1 downto 0);
signal wr_addr : out std_logic_vector(REG_WIDTH-1 downto 0);
signal wr_data : out std_logic_vector(REG_WIDTH-1 downto 0);
signal wr_data : out std_logic_vector(XLEN-1 downto 0);
signal we : out std_logic;
signal flush : out std_logic;
......@@ -83,12 +83,12 @@ architecture tb of riscv_decode_tb is
signal pc_o : in std_logic_vector(XLEN-1 downto 0);
signal imm : in std_logic_vector(XLEN-1 downto 0);
signal test_instruction : in std_logic_vector(XLEN-1 downto 0);
signal test_pc_i : in std_logic_vector(XLEN-1 downto 0);
signal test_wr_addr : in std_logic_vector(REG_WIDTH-1 downto 0);
signal test_wr_data : in std_logic_vector(REG_WIDTH-1 downto 0);
signal test_we : in std_logic;
signal test_flush : in std_logic;
constant test_instruction : in std_logic_vector(XLEN-1 downto 0);
constant test_pc_i : in std_logic_vector(XLEN-1 downto 0);
constant test_wr_addr : in std_logic_vector(REG_WIDTH-1 downto 0);
constant test_wr_data : in std_logic_vector(XLEN-1 downto 0);
constant test_we : in std_logic;
constant test_flush : in std_logic;
constant expected_rs1_data : in std_logic_vector(XLEN-1 downto 0);
constant expected_rs2_data : in std_logic_vector(XLEN-1 downto 0);
......@@ -173,6 +173,7 @@ begin
-- Main TB process
p_main : process is
constant DUMMY_DATA : std_logic_vector(XLEN-1 downto 0) := (3 downto 0 => "1010", others => '1');
constant DUMMY_REG_ADDR : std_logic_vector(REG_WIDTH-1 downto 0) := (others => '1');
constant EXAMPLE_PC : std_logic_vector(XLEN-1 downto 0) := (3 downto 0 => "1010", others => '1');
begin
......@@ -193,12 +194,12 @@ begin
report "Write all registers except 0x00";
for i in 1 to 2**(REG_WIDTH)-1 loop
write_reg(
addr_w => addr_w,
data_w => data_w,
wr_addr => wr_addr,
wr_data => wr_data,
we => we,
test_addr_w => std_logic_vector(to_unsigned(i, addr_w)),
test_data_w => std_logic_vector(to_unsigned(i + 3, data_w)),
test_wr_addr => std_logic_vector(to_unsigned(i, wr_addr'length)),
test_wr_data => std_logic_vector(to_unsigned(i + 3, wr_data'length)),
period => PERIOD
);
......@@ -212,7 +213,7 @@ begin
instruction, pc_i, wr_addr, wr_data, we, flush, rs1_data, rs2_data,
shamt, arith, sign, jump, branch, pc_o, imm,
test_instruction => "000000000000" & std_logic_vector(to_unsigned(0, REG_WIDTH)) & FUNCT3_ADD & OPCODE_ALU_I_TYPE,
test_instruction => "000000000000" & std_logic_vector(to_unsigned(0, REG_WIDTH)) & FUNCT3_ADD & DUMMY_REG_ADDR & OPCODE_ALU_I_TYPE,
test_pc_i => EXAMPLE_PC,
test_wr_addr => (others => '-'),
test_wr_data => (others => '-'),
......@@ -222,13 +223,13 @@ begin
expected_rs1_data => (others => '0'),
expected_rs2_data => (others => '-'),
expected_shamt => (others => '-'),
expected_arith => (others => '-'),
expected_sign => (others => '-'),
expected_jump => (others => '-'),
expected_branch => (others => '-'),
expected_arith => '-',
expected_sign => '-',
expected_jump => '-',
expected_branch => '-',
expected_pc_o => EXAMPLE_PC,
expected_imm => (others => '0'),
PERIOD
period => PERIOD
);
for i in 1 to 2**(REG_WIDTH)-2 loop
......@@ -237,7 +238,7 @@ begin
instruction, pc_i, wr_addr, wr_data, we, flush, rs1_data, rs2_data,
shamt, arith, sign, jump, branch, pc_o, imm,
test_instruction => "000000000000" & std_logic_vector(to_unsigned(i, REG_WIDTH)) & FUNCT3_ADD & OPCODE_ALU_I_TYPE,
test_instruction => "000000000000" & std_logic_vector(to_unsigned(i, REG_WIDTH)) & FUNCT3_ADD & DUMMY_REG_ADDR & OPCODE_ALU_I_TYPE,
test_pc_i => EXAMPLE_PC,
test_wr_addr => (others => '-'),
test_wr_data => (others => '-'),
......@@ -247,13 +248,13 @@ begin
expected_rs1_data => std_logic_vector(to_unsigned(i+3, rs1_data'length)),
expected_rs2_data => (others => '-'),
expected_shamt => (others => '-'),
expected_arith => (others => '-'),
expected_sign => (others => '-'),
expected_jump => (others => '-'),
expected_branch => (others => '-'),
expected_arith => '-',
expected_sign => '-',
expected_jump => '-',
expected_branch => '-',
expected_pc_o => EXAMPLE_PC,
expected_imm => (others => '0'),
PERIOD
period => PERIOD
);
end loop;
......@@ -264,7 +265,7 @@ begin
instruction, pc_i, wr_addr, wr_data, we, flush, rs1_data, rs2_data,
shamt, arith, sign, jump, branch, pc_o, imm,
test_instruction => "11110000111100001111" & "00011" & OPCODE_LUI,
test_instruction => "11110000111100001111" & DUMMY_REG_ADDR & OPCODE_LUI,
test_pc_i => EXAMPLE_PC,
test_wr_addr => (others => '-'),
test_wr_data => (others => '-'),
......@@ -274,18 +275,63 @@ begin
expected_rs1_data => (others => '-'),
expected_rs2_data => (others => '-'),
expected_shamt => (others => '-'),
expected_arith => (others => '-'),
expected_sign => (others => '-'),
expected_jump => (others => '-'),
expected_branch => (others => '-'),
expected_arith => '0',
expected_sign => '0',
expected_jump => '0',
expected_branch => '0',
expected_pc_o => EXAMPLE_PC,
expected_imm => (XLEN-1 downto 12 => "11110000111100001111", others => '0'),
PERIOD
period => PERIOD
);
-- JAL
test_vector(
instruction, pc_i, wr_addr, wr_data, we, flush, rs1_data, rs2_data,
shamt, arith, sign, jump, branch, pc_o, imm,
test_instruction => "11110000111100001111" & DUMMY_DEST_REG & OPCODE_JAL,
test_pc_i => EXAMPLE_PC,
test_wr_addr => (others => '-'),
test_wr_data => (others => '-'),
test_we => '0',
test_flush => '0',
expected_rs1_data => (others => '-'),
expected_rs2_data => (others => '-'),
expected_shamt => (others => '-'),
expected_arith => '0',
expected_sign => '0',
expected_jump => '1',
expected_branch => '0',
expected_pc_o => EXAMPLE_PC,
expected_imm => (XLEN-1 downto 12 => "11110000111100001111", others => '0'),
period => PERIOD
);
-- JALR
test_vector(
instruction, pc_i, wr_addr, wr_data, we, flush, rs1_data, rs2_data,
shamt, arith, sign, jump, branch, pc_o, imm,
test_instruction => "111100001111" & DUMMY_REG_ADDR & FUNCT3_JALR & DUMMY_DEST_REG & OPCODE_JALR,
test_pc_i => EXAMPLE_PC,
test_wr_addr => (others => '-'),
test_wr_data => (others => '-'),
test_we => '0',
test_flush => '0',
expected_rs1_data => (others => '-'),
expected_rs2_data => (others => '-'),
expected_shamt => (others => '-'),
expected_arith => '-',
expected_sign => '-',
expected_jump => '-',
expected_branch => '-',
expected_pc_o => EXAMPLE_PC,
expected_imm => (XLEN-1 downto 12 => "111100001111", others => '0'),
period => PERIOD
);
-- BEQ
......
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