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Commit 56408c9a authored by Yann Roberge's avatar Yann Roberge
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Version préliminaire bugguée du TB du Decode

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sources/riscv_decode.vhd
+ 12
− 0
View file @ 56408c9a
......@@ -80,6 +80,18 @@ begin
-- DEBUG:
o_rs1_data <= (others => '1');
o_rs2_data <= (others => '1');
o_shamt <= (others => '1');
o_arith <= '1';
o_sign <= '1';
o_jump <= '1';
o_branch <= '1';
o_pc <= (others => '1');
o_imm <= (others => '1');
-- Références:
-- Écrire le registre pointé
......
sources/riscv_decode_tb.vhd
+ 159
− 95
View file @ 56408c9a
......@@ -24,31 +24,27 @@ end riscv_decode_tb;
architecture tb of riscv_decode_tb is
-- Entrées/Sorties du DUT
instruction : std_logic_vector(XLEN-1 downto 0);
pc_i : std_logic_vector(XLEN-1 downto 0);
wr_addr : std_logic_vector(REG_WIDTH-1 downto 0);
wr_data : std_logic_vector(REG_WIDTH-1 downto 0);
we : std_logic;
flush : std_logic;
rstn : std_logic;
clk : std_logic;
rs1_data : std_logic_vector(XLEN-1 downto 0);
rs2_data : std_logic_vector(XLEN-1 downto 0);
shamt : std_logic_vector(SHAMT_WIDTH-1 downto 0);
arith : std_logic;
sign : std_logic;
jump : std_logic;
branch : std_logic;
pc_o : std_logic_vector(XLEN-1 downto 0);
imm : std_logic_vector(XLEN-1 downto 0));
signal instruction : std_logic_vector(XLEN-1 downto 0);
signal pc_i : std_logic_vector(XLEN-1 downto 0);
signal wr_addr : std_logic_vector(REG_WIDTH-1 downto 0);
signal wr_data : std_logic_vector(REG_WIDTH-1 downto 0);
signal we : std_logic;
signal flush : std_logic;
signal rstn : std_logic;
signal clk : std_logic;
signal rs1_data : std_logic_vector(XLEN-1 downto 0);
signal rs2_data : std_logic_vector(XLEN-1 downto 0);
signal shamt : std_logic_vector(SHAMT_WIDTH-1 downto 0);
signal arith : std_logic;
signal sign : std_logic;
signal jump : std_logic;
signal branch : std_logic;
signal pc_o : std_logic_vector(XLEN-1 downto 0);
signal imm : std_logic_vector(XLEN-1 downto 0);
-- Write to a register, no checking of what's coming out
-- TODO: Adapter
procedure write_reg (
signal rstn : out std_logic;
signal addr_ra : out std_logic_vector(REG_WIDTH-1 downto 0);
signal addr_rb : out std_logic_vector(REG_WIDTH-1 downto 0);
signal addr_w : out std_logic_vector(REG_WIDTH-1 downto 0);
signal data_w : out std_logic_vector(XLEN-1 downto 0);
signal we : out std_logic;
......@@ -58,35 +54,84 @@ architecture tb of riscv_decode_tb is
constant period : in time) is
begin
rstn <= '1';
addr_ra <= (others => '-');
addr_rb <= (others => '-');
addr_w <= test_addr_w;
data_w <= test_data_w;
we <= '1';
wait for period;
report "Wrote " & to_string(data_w) & " to reg " & to_string(addr_w);
addr_w <= (others => '-');
data_w <= (others => '-');
we <= '0';
wait for period;
end procedure write_reg;
-- Procédure pour un vecteur de test
-- TODO: Adapter
procedure test_vector (
constant period : in time) is
begin
wait for period;
signal instruction : out std_logic_vector(XLEN-1 downto 0);
signal pc_i : out std_logic_vector(XLEN-1 downto 0);
signal wr_addr : out std_logic_vector(REG_WIDTH-1 downto 0);
signal wr_data : out std_logic_vector(REG_WIDTH-1 downto 0);
signal we : out std_logic;
signal flush : out std_logic;
signal rs1_data : in std_logic_vector(XLEN-1 downto 0);
signal rs2_data : in std_logic_vector(XLEN-1 downto 0);
signal shamt : in std_logic_vector(SHAMT_WIDTH-1 downto 0);
signal arith : in std_logic;
signal sign : in std_logic;
signal jump : in std_logic;
signal branch : in std_logic;
signal pc_o : in std_logic_vector(XLEN-1 downto 0);
signal imm : in std_logic_vector(XLEN-1 downto 0);
signal test_instruction : in std_logic_vector(XLEN-1 downto 0);
signal test_pc_i : in std_logic_vector(XLEN-1 downto 0);
signal test_wr_addr : in std_logic_vector(REG_WIDTH-1 downto 0);
signal test_wr_data : in std_logic_vector(REG_WIDTH-1 downto 0);
signal test_we : in std_logic;
signal test_flush : in std_logic;
constant expected_rs1_data : in std_logic_vector(XLEN-1 downto 0);
constant expected_rs2_data : in std_logic_vector(XLEN-1 downto 0);
constant expected_shamt : in std_logic_vector(SHAMT_WIDTH-1 downto 0);
constant expected_arith : in std_logic;
constant expected_sign : in std_logic;
constant expected_jump : in std_logic;
constant expected_branch : in std_logic;
constant expected_pc_o : in std_logic_vector(XLEN-1 downto 0);
constant expected_imm : in std_logic_vector(XLEN-1 downto 0);
assert data_ra = expected_ra
report "REGISTER A DIFFERS FROM EXPECTED" severity error;
assert data_rb = expected_rb
report "REGISTER B DIFFERS FROM EXPECTED" severity error;
constant period : in time) is
begin
-- Set test signals
instruction <= test_instruction;
pc_i <= test_pc_i;
wr_addr <= test_wr_addr;
wr_data <= test_wr_data;
we <= test_we;
flush <= test_flush;
-- Wait a cycle
wait for period;
-- Assert all outputs are what we expect
assert rs1_data = expected_rs1_data
report "RS1_DATA DIFFERS FROM EXPECTED" severity error;
assert rs2_data = expected_rs2_data
report "RS2_DATA DIFFERS FROM EXPECTED" severity error;
assert shamt = expected_shamt
report "SHAMT DIFFERS FROM EXPECTED" severity error;
assert arith = expected_arith
report "ARITH DIFFERS FROM EXPECTED" severity error;
assert sign = expected_sign
report "SIGN DIFFERS FROM EXPECTED" severity error;
assert jump = expected_jump
report "JUMP DIFFERS FROM EXPECTED" severity error;
assert branch = expected_branch
report "BRANCH DIFFERS FROM EXPECTED" severity error;
assert pc_o = expected_pc_o
report "PC_O DIFFERS FROM EXPECTED" severity error;
assert imm = expected_imm
report "IMM DIFFERS FROM EXPECTED" severity error;
end procedure test_vector;
......@@ -97,7 +142,7 @@ begin
-- Instanciation du DUT
dut: entity work.riscv_decode
port map (
i_instruction => instruction,
i_instruction => instruction,
i_pc => pc_i,
i_wr_addr => wr_addr,
i_wr_data => wr_data,
......@@ -128,16 +173,17 @@ begin
-- Main TB process
p_main : process is
constant DUMMY_DATA : std_logic_vector(XLEN-1 downto 0) := (3 downto 0 => "1010", others => '1');
constant EXAMPLE_PC : std_logic_vector(XLEN-1 downto 0) := (3 downto 0 => "1010", others => '1');
begin
-- Tests des cas représentatif
report "BEGIN SIMULATION";
--rstn <= '0';
--addr_ra <= (others => '-');
--addr_rb <= (others => '-');
--addr_w <= (others => '-');
--data_w <= (others => '-');
--we <= '-';
instruction <= (others => '-');
pc_i <= (others => '-');
wr_data <= (others => '-');
we <= '-';
flush <= '0';
rstn <= '0';
wait for PERIOD;
rstn <= '1';
wait for 2*PERIOD;
......@@ -147,16 +193,12 @@ begin
report "Write all registers except 0x00";
for i in 1 to 2**(REG_WIDTH)-1 loop
write_reg(
rstn => rstn,
addr_ra => addr_ra,
addr_rb => addr_rb,
addr_w => addr_w,
data_w => data_w,
we => we,
test_addr_w => std_logic_vector(to_unsigned(i, REG_WIDTH)),
test_data_w => std_logic_vector(to_unsigned(i + 3, XLEN)),
test_addr_w => std_logic_vector(to_unsigned(i, addr_w)),
test_data_w => std_logic_vector(to_unsigned(i + 3, data_w)),
period => PERIOD
);
......@@ -165,59 +207,81 @@ begin
-- Read back all registers
-- TODO: Adapter mais le laisser faire la même chose
report "Read back all registers";
test_vector( -- special case for register 0
rstn => rstn,
addr_ra => addr_ra,
addr_rb => addr_rb,
addr_w => addr_w,
data_w => data_w,
we => we,
data_ra => data_ra,
data_rb => data_rb,
test_addr_ra => std_logic_vector(to_unsigned(0, addr_ra'length)),
test_addr_rb => std_logic_vector(to_unsigned(0, addr_rb'length)),
test_addr_w => (others => '-'),
test_data_w => (others => '-'),
test_we => '0',
expected_ra => (others => '0'),
expected_rb => (others => '0'),
period => PERIOD
);
-- ADDI 0 to reg[0] specifically, check result
test_vector(
instruction, pc_i, wr_addr, wr_data, we, flush, rs1_data, rs2_data,
shamt, arith, sign, jump, branch, pc_o, imm,
test_instruction => "000000000000" & std_logic_vector(to_unsigned(0, REG_WIDTH)) & FUNCT3_ADD & OPCODE_ALU_I_TYPE,
test_pc_i => EXAMPLE_PC,
test_wr_addr => (others => '-'),
test_wr_data => (others => '-'),
test_we => '0',
test_flush => '0',
expected_rs1_data => (others => '0'),
expected_rs2_data => (others => '-'),
expected_shamt => (others => '-'),
expected_arith => (others => '-'),
expected_sign => (others => '-'),
expected_jump => (others => '-'),
expected_branch => (others => '-'),
expected_pc_o => EXAMPLE_PC,
expected_imm => (others => '0'),
PERIOD
);
for i in 1 to 2**(REG_WIDTH)-2 loop
-- ADDI 0 to reg[i], check result
test_vector(
rstn => rstn,
addr_ra => addr_ra,
addr_rb => addr_rb,
addr_w => addr_w,
data_w => data_w,
we => we,
data_ra => data_ra,
data_rb => data_rb,
test_addr_ra => std_logic_vector(to_unsigned(i, addr_ra'length)),
test_addr_rb => std_logic_vector(to_unsigned(i+1, addr_rb'length)),
test_addr_w => (others => '-'),
test_data_w => (others => '-'),
test_we => '0',
expected_ra => std_logic_vector(to_unsigned(i+3, data_ra'length)),
expected_rb => std_logic_vector(to_unsigned(i+4, data_rb'length)),
period => PERIOD
instruction, pc_i, wr_addr, wr_data, we, flush, rs1_data, rs2_data,
shamt, arith, sign, jump, branch, pc_o, imm,
test_instruction => "000000000000" & std_logic_vector(to_unsigned(i, REG_WIDTH)) & FUNCT3_ADD & OPCODE_ALU_I_TYPE,
test_pc_i => EXAMPLE_PC,
test_wr_addr => (others => '-'),
test_wr_data => (others => '-'),
test_we => '0',
test_flush => '0',
expected_rs1_data => std_logic_vector(to_unsigned(i+3, rs1_data'length)),
expected_rs2_data => (others => '-'),
expected_shamt => (others => '-'),
expected_arith => (others => '-'),
expected_sign => (others => '-'),
expected_jump => (others => '-'),
expected_branch => (others => '-'),
expected_pc_o => EXAMPLE_PC,
expected_imm => (others => '0'),
PERIOD
);
end loop;
report "Test every instruction in supported ISA";
-- LUI: registre 0x03 <- pattern 0101 répété sur 20 bits
test_vector(
instruction, pc_i, wr_addr, wr_data, we, flush, rs1_data, rs2_data,
shamt, arith, sign, jump, branch, pc_o, imm,
test_instruction => "11110000111100001111" & "00011" & OPCODE_LUI,
test_pc_i => EXAMPLE_PC,
test_wr_addr => (others => '-'),
test_wr_data => (others => '-'),
test_we => '0',
test_flush => '0',
expected_rs1_data => (others => '-'),
expected_rs2_data => (others => '-'),
expected_shamt => (others => '-'),
expected_arith => (others => '-'),
expected_sign => (others => '-'),
expected_jump => (others => '-'),
expected_branch => (others => '-'),
expected_pc_o => EXAMPLE_PC,
expected_imm => (XLEN-1 downto 12 => "11110000111100001111", others => '0'),
PERIOD
);
-- JAL
......
sources/riscv_pkg.vhd
+ 34
− 0
View file @ 56408c9a
......@@ -28,6 +28,40 @@ package riscv_pkg is
constant SHAMT_L : natural := 20;
constant SHAMT_WIDTH : natural := SHAMT_H-SHAMT_L+1;
-- ISA Opcodes
constant OPCODE_LUI : std_logic_vector := "0110111";
constant OPCODE_JAL : std_logic_vector := "1101111";
constant OPCODE_JALR : std_logic_vector := "1100111";
constant OPCODE_BEQ : std_logic_vector := "1100011";
constant OPCODE_LW : std_logic_vector := "0000011";
constant OPCODE_SW : std_logic_vector := "0100011";
constant OPCODE_ALU_I_TYPE : std_logic_vector := "0010011"; -- All I-types with ALU
constant OPCODE_ALU_R_TYPE : std_logic_vector := "0110011"; -- All R-types with ALU
-- FUNCT7 field
-- Identifies SUB and Arithmetic shifts
constant FUNCT7_SUB_ARITH_SH : std_logic_vector := "0100000";
constant FUNCT7_GENERIC : std_logic_vector := "0000000";
-- FUNCT3 field
-- Identifies instruction more specifically than the opcode
-- The field is the same for the I-type and R-type versions of a same operation
-- The field is the same for logic and arithmetic shifts of the same direction (L, R)
-- The field is the same for ADD and SUB (distriminated with FUNCT7)
constant FUNCT3_JALR : std_logic_vector := "000";
constant FUNCT3_BEQ : std_logic_vector := "000";
constant FUNCT3_LW : std_logic_vector := "010";
constant FUNCT3_SW : std_logic_vector := "010";
constant FUNCT3_ADD : std_logic_vector := "000";
constant FUNCT3_SLT : std_logic_vector := "010";
constant FUNCT3_SLTU : std_logic_vector := "011";
constant FUNCT3_XOR : std_logic_vector := "100";
constant FUNCT3_OR : std_logic_vector := "110";
constant FUNCT3_AND : std_logic_vector := "111";
constant FUNCT3_SL : std_logic_vector := "001";
constant FUNCT3_SR : std_logic_vector := "101";
constant FUNCT3_SUB : std_logic_vector := "000";
------------------------------------------------------------------------------
-- ALU
------------------------------------------------------------------------------
......
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