Modifs mineures

sources/riscv_decode_tb.vhd

@@ -137,6 +137,14 @@ architecture tb of riscv_decode_tb is
 
   constant PERIOD : time := 10 ns;
 
+  -- Used to set the expected IMM as a function of intruction and its type
+  signal inst : std_logic_vector(XLEN-1 downto 0);
+
+  signal i_imm : std_logic_vector(XLEN-1 downto 0);
+  signal s_imm : std_logic_vector(XLEN-1 downto 0);
+  signal b_imm : std_logic_vector(XLEN-1 downto 0);
+  signal u_imm : std_logic_vector(XLEN-1 downto 0);
+  signal j_imm : std_logic_vector(XLEN-1 downto 0);
 begin
 
   -- Instanciation du DUT
@@ -170,11 +178,25 @@ begin
     wait for PERIOD/2;
   end process drive_clk;
 
+  -- Set expected IMM as a function of the instruction type
+  set_imm : process (inst) is
+  begin
+    i_imm <= (others => '0');
+    s_imm <= (others => '0');
+    b_imm <= (others => '0');
+    u_imm <= (others => '0');
+
+    j_imm(31 downto 20) <= (others => inst(31));
+    j_imm(19 downto 0) <= inst(19 downto 12) & inst(20) & inst(30 downto 25) & inst(24 downto 21) & '0';
+  end process set_imm;
+
   -- Main TB process
   p_main : process is
     constant DUMMY_DATA : std_logic_vector(XLEN-1 downto 0) := (3 downto 0 => "1010", others => '1');
     constant DUMMY_REG_ADDR : std_logic_vector(REG_WIDTH-1 downto 0) := (others => '1');
+    constant DUMMY_DEST_REG : std_logic_vector(REG_WIDTH-1 downto 0) := (1 downto 0 => "11", others => '0');
     constant EXAMPLE_PC : std_logic_vector(XLEN-1 downto 0) := (3 downto 0 => "1010", others => '1');
+
   begin
 
     -- Tests des cas représentatif
@@ -185,12 +207,13 @@ begin
     we          <= '-';
     flush <= '0';
     rstn <= '0';
+
+    inst <= (others => '-');
     wait for PERIOD;
     rstn <= '1';
     wait for 2*PERIOD;
 
     -- Write all registers
-    -- TODO: Adapter mais le laisser faire la même chose
     report "Write all registers except 0x00";
     for i in 1 to 2**(REG_WIDTH)-1 loop
       write_reg(
@@ -206,7 +229,6 @@ begin
     end loop;
 
     -- Read back all registers
-    -- TODO: Adapter mais le laisser faire la même chose
     report "Read back all registers";
     -- ADDI 0 to reg[0] specifically, check result
     test_vector(
@@ -237,7 +259,7 @@ begin
       test_vector(
         instruction, pc_i, wr_addr, wr_data, we, flush, rs1_data, rs2_data,
         shamt, arith, sign, jump, branch, pc_o, imm,
-  
+
         test_instruction => "000000000000" & std_logic_vector(to_unsigned(i, REG_WIDTH)) & FUNCT3_ADD & DUMMY_REG_ADDR & OPCODE_ALU_I_TYPE,
         test_pc_i        => EXAMPLE_PC,
         test_wr_addr     => (others => '-'),
@@ -258,7 +280,7 @@ begin
       );
     end loop;
 
-    report "Test every instruction in supported ISA"; 
+    report "Test every instruction in supported ISA";
 
     -- LUI: registre 0x03 <- pattern 0101 répété sur 20 bits
     test_vector(
@@ -285,6 +307,7 @@ begin
     );
 
     -- JAL
+    inst <= "11110000111100001111" & DUMMY_DEST_REG & OPCODE_JAL;
     test_vector(
       instruction, pc_i, wr_addr, wr_data, we, flush, rs1_data, rs2_data,
       shamt, arith, sign, jump, branch, pc_o, imm,
@@ -304,7 +327,7 @@ begin
       expected_jump     => '1',
       expected_branch   => '0',
       expected_pc_o     => EXAMPLE_PC,
-      expected_imm      => (XLEN-1 downto 12 => "11110000111100001111", others => '0'),
+      expected_imm      => j_imm,
       period => PERIOD
     );
 
@@ -323,17 +346,39 @@ begin
       expected_rs1_data => (others => '-'),
       expected_rs2_data => (others => '-'),
       expected_shamt    => (others => '-'),
-      expected_arith    => '-',
-      expected_sign     => '-',
-      expected_jump     => '-',
-      expected_branch   => '-',
+      expected_arith    => '0',
+      expected_sign     => '0',
+      expected_jump     => '1',
+      expected_branch   => '0',
       expected_pc_o     => EXAMPLE_PC,
-      expected_imm      => (XLEN-1 downto 12 => "111100001111", others => '0'),
+      expected_imm      => (others => '0'),
       period => PERIOD
     );
 
-
     -- BEQ
+    test_vector(
+      instruction, pc_i, wr_addr, wr_data, we, flush, rs1_data, rs2_data,
+      shamt, arith, sign, jump, branch, pc_o, imm,
+
+      test_instruction => "111100001111" & DUMMY_REG_ADDR & FUNCT3_JALR & DUMMY_DEST_REG & OPCODE_JALR,
+      test_pc_i        => EXAMPLE_PC,
+      test_wr_addr     => (others => '-'),
+      test_wr_data     => (others => '-'),
+      test_we          => '0',
+      test_flush       => '0',
+
+      expected_rs1_data => (others => '-'),
+      expected_rs2_data => (others => '-'),
+      expected_shamt    => (others => '-'),
+      expected_arith    => '0',
+      expected_sign     => '0',
+      expected_jump     => '1',
+      expected_branch   => '0',
+      expected_pc_o     => EXAMPLE_PC,
+      expected_imm      => (others => '0'),
+      period => PERIOD
+    );
+
 
     -- LW