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Yann Roberge
lab-2
Commits
07e78744
Commit
07e78744
authored
3 years ago
by
8304_9
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Déplacé les constantes de l'additionneur et ajouté les constantes de l'ALU
parent
20388e87
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sources/riscv_adder.vhd
+2
-8
2 additions, 8 deletions
sources/riscv_adder.vhd
sources/riscv_pkg.vhd
+17
-0
17 additions, 0 deletions
sources/riscv_pkg.vhd
with
19 additions
and
8 deletions
sources/riscv_adder.vhd
+
2
−
8
View file @
07e78744
...
...
@@ -47,18 +47,12 @@ architecture beh of riscv_adder is
signal
temp_carry2
:
std_logic_vector
(
N
-1
downto
0
);
signal
ored_carries
:
std_logic_vector
(
N
-1
downto
0
);
-- Bits de contrôles
constant
OP_UNSIGNED
:
std_logic
:
=
'0'
;
constant
OP_SIGNED
:
std_logic
:
=
'1'
;
constant
OP_ADD
:
std_logic
:
=
'0'
;
constant
OP_SUBTRACT
:
std_logic
:
=
'1'
;
begin
sign_extend
:
process
(
all
)
is
begin
if
(
i_sign
=
OP
_UNSIGNED
)
then
if
(
i_sign
=
SIGN
_UNSIGNED
)
then
a_ext
<=
'0'
&
i_a
;
b_ext
<=
'0'
&
i_b
;
else
...
...
@@ -71,7 +65,7 @@ begin
b_compl2
<=
std_logic_vector
(
unsigned
(
not
(
b_ext
))
+
1
);
-- Addition ou soustraction
b_operand
<=
b_compl2
when
i_sub
=
OP
_SUBTRACT
else
b_ext
;
b_operand
<=
b_compl2
when
i_sub
=
ARITH
_SUBTRACT
else
b_ext
;
gen_half_adders_top
:
for
i
in
0
to
N
generate
...
...
This diff is collapsed.
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sources/riscv_pkg.vhd
+
17
−
0
View file @
07e78744
...
...
@@ -32,6 +32,23 @@ package riscv_pkg is
-- ALU
------------------------------------------------------------------------------
constant
ALUOP_WIDTH
:
natural
:
=
3
;
constant
ALUOP_SH_RIGHT
:
std_logic_vector
:
=
"000"
;
-- 0
constant
ALUOP_SH_LEFT
:
std_logic_vector
:
=
"001"
;
-- 1
constant
ALUOP_SLT
:
std_logic_vector
:
=
"010"
;
-- 2
constant
ALUOP_ADD
:
std_logic_vector
:
=
"011"
;
-- 3
constant
ALUOP_AND
:
std_logic_vector
:
=
"100"
;
-- 4
constant
ALUOP_XOR
:
std_logic_vector
:
=
"101"
;
-- 5
constant
ALUOP_OR
:
std_logic_vector
:
=
"110"
;
-- 6
-- Bits de contrôles
constant
SIGN_UNSIGNED
:
std_logic
:
=
'0'
;
constant
SIGN_SIGNED
:
std_logic
:
=
'1'
;
constant
ARITH_ADD
:
std_logic
:
=
'0'
;
constant
ARITH_SUBTRACT
:
std_logic
:
=
'1'
;
constant
SHIFT_LOGIC
:
std_logic
:
=
'0'
;
constant
SHIFT_ARITH
:
std_logic
:
=
'1'
;
------------------------------------------------------------------------------
-- COMPONENTS
...
...
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