riscv_pc.vhd

-------------------------------------------------------------------------------
-- Project  ELE8304 : Circuits intégrés à très grande échelle
-------------------------------------------------------------------------------
-- File     counter.vhd
-- Authors  Titouan Luard <luardtitouan@gmail.com> 
--          Yann Roberge <yann.roberge@polymtl.ca> 
-- Lab      GRM - Polytechnique Montreal
-- Date     2021-10-29
-------------------------------------------------------------------------------
-- Brief    Single-bit half-adder with carry out
------------------------------------------------------------------------
-------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;



library work;
use work.riscv_pkg.all;

entity riscv_pc is
  generic ( XLEN      : positive := 32;
  RESET_VECTOR : std_logic_vector(XLEN-1 downto 0) := (others => '0'));
  port (
    i_clk :       in std_logic;
    i_rstn :      in std_logic;
    i_stall :     in std_logic;
    i_transfert : in std_logic;
    i_target :    in std_logic_vector(XLEN-1 downto 0);
    o_pc :        out std_logic_vector(XLEN-1 downto 0));
end entity riscv_pc;



architecture beh of riscv_pc is

signal o_add : std_logic_vector(XLEN downto 0);

begin

adder: entity work.riscv_adder
  generic MAP (N => XLEN)
    port MAP (
      i_a    =>   o_pc,
      i_b    =>   std_logic_vector(to_unsigned(4,XLEN)),
      i_sign =>   '0',
      i_sub  =>   '0',
      o_sum  =>  o_add);

count: 
process (i_clk, i_rstn) is
  begin
  if i_rstn = '0' then
    o_pc <= std_logic_vector(RESET_VECTOR) ;
  
  elsif i_rstn= '1' and rising_edge(i_clk) then
  
    if i_stall = '1' then
      o_pc <= o_pc;
  
    elsif i_transfert = '1' then
      o_pc <= i_target;
    
    elsif i_transfert = '0' and i_stall = '0' then
      o_pc <= o_add(XLEN-1 downto 0);

    else
      o_pc <= o_pc;
    end if;
  end if;
  
end process count;


end architecture beh;