Program counter terminé et normalement testé

sources/riscv_pc.vhd

@@ -34,18 +34,18 @@ end entity riscv_pc;
 
 architecture beh of riscv_pc is
 
-signal o_add : std_logic_vector(XLEN-1 downto 0);
+signal o_add : std_logic_vector(XLEN downto 0);
 
 begin
 
 adder: entity work.riscv_adder
-  generic MAP (N => XLEN-1)
+  generic MAP (N => XLEN)
     port MAP (
       i_a    =>   o_pc ,
-      i_b    =>   std_logic_vector(to_unsigned(4,XLEN-1)) ,
+      i_b    =>   std_logic_vector(to_unsigned(4,XLEN)) ,
       i_sign =>   '0' ,
       i_sub  =>   '0' ,
-      o_sum  =>  o_add );
+      o_sum =>  o_add );
 count: 
 process (i_clk, i_rstn) is
   begin
@@ -61,7 +61,7 @@ process (i_clk, i_rstn) is
     o_pc <= i_target ;
     
     elsif i_transfert = '0' then
-      o_pc<= o_add ;
+      o_pc<= o_add(XLEN-1 downto 0)  ;
 
     else
       o_pc <= o_pc ;

sources/riscv_pc_tb.vhd

@@ -51,6 +51,14 @@ begin
       o_pc => pc
     );
 
+  drive_clk : process
+  begin
+    clk <= '0';
+    wait for PERIOD/2;
+    clk <= '1';
+    wait for PERIOD/2;
+  end process drive_clk;
+
   -- Main TB process
   p_main : process
   begin
@@ -62,7 +70,7 @@ begin
     rstn <= '0' ;
     expected_result<=(others => '0');
     wait for PERIOD;
-    assert pc = expected_result;
+    assert pc = expected_result
       report "init error" severity error;
     wait for PERIOD;
 
@@ -71,7 +79,7 @@ begin
     wait for PERIOD; 
     transfert<= '0';
     expected_result<=(2 downto 0 => "100",others => '0');
-    assert pc = expected_result;
+    assert pc = expected_result
       report "adder error" severity error;
     wait for PERIOD;
 
@@ -79,14 +87,15 @@ begin
     transfert <= '1';
     target <= (0 downto 0 =>'1', others => '0' );
     expected_result<=(0 downto 0 =>'1', others => '0');
-    assert pc =  expected_result;
+    assert pc =  expected_result
       report "target error" severity error;
     wait for PERIOD;
     report "reset";
+    rstn <= '0' ;
     expected_result<=(others => '0');
     wait for PERIOD;
-    assert pc = expected_result;
-      report "init error" severity error;
+    assert pc = expected_result
+      report "reset error" severity error;
     wait for PERIOD;
 
     report "SIMULATION DONE";