Newer
Older
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
-------------------------------------------------------------------------------
-- Project ELE8304 : Circuits intégrés à très grande échelle
-------------------------------------------------------------------------------
-- File riscv_adder.vhd
-- Authors Titouan Luard <luardtitouan@gmail.com>
-- Yann Roberge <yann.roberge@polymtl.ca>
-- Lab ELE8304-9
-- Date 2021-11-13
-------------------------------------------------------------------------------
-- Brief Mini RISC-V ALU capable of performing add, shift and bitwise
-- AND, OR & XOR operations
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.riscv_pkg.all;
entity riscv_alu is
port (
i_arith : in std_logic;
i_sign : in std_logic;
i_opcode : in std_logic_vector(ALUOP_WIDTH-1 downto 0);
i_shamt : in std_logic_vector(SHAMT_WIDTH-1 downto 0);
i_src1 : in std_logic_vector(XLEN-1 downto 0);
i_src2 : in std_logic_vector(XLEN-1 downto 0);
o_res : out std_logic_vector(XLEN-1 downto 0));
end entity riscv_alu;
architecture beh of riscv_alu is
-- Signaux en entrée du multiplexeur
signal shifter_result : std_logic_vector(XLEN-1 downto 0);
signal adder_result : std_logic_vector(XLEN downto 0);
alias adder_result_sign : std_logic is adder_result(XLEN-1);
signal and_result : std_logic_vector(XLEN-1 downto 0);
signal xor_result : std_logic_vector(XLEN-1 downto 0);
signal or_result : std_logic_vector(XLEN-1 downto 0);
begin
-- Instanciation de l'additionneur
adder: entity work.riscv_adder
generic map (
N => XLEN)
port map (
i_a => i_src1,
i_b => i_src2,
i_sign => i_sign,
i_sub => i_arith,
o_sum => adder_result);
-- Barrel Shifter
shifter: entity work.shifter
port map (
i_shamt => i_shamt,
i_src1 => i_src1,
i_arith => i_arith,
i_opcode => i_opcode,
o_sh => shifter_result);
-- Unité logique
and_result <= i_src1 and i_src2;
xor_result <= i_src1 xor i_src2;
or_result <= i_src1 or i_src2;
-- Étage de multiplexeur
with i_opcode select o_res <=
shifter_result when ALUOP_SH_RIGHT,
shifter_result when ALUOP_SH_LEFT,
(0 => adder_result_sign, others=> '0') when ALUOP_SLT,
adder_result(XLEN-1 downto 0) when ALUOP_ADD,
and_result when ALUOP_AND,
xor_result when ALUOP_XOR,
or_result when ALUOP_OR,
(others => '0') when others;
end architecture beh;