Newer
Older
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
-------------------------------------------------------------------------------
-- Project ELE8304 : Circuits intégrés à très grande échelle
-------------------------------------------------------------------------------
-- File shifter_tb.vhd
-- Authors Titouan Luard <luardtitouan@gmail.com>
-- Yann Roberge <yann.roberge@polymtl.ca>
-- Lab GRM - Polytechnique Montreal
-- Date 2021-10-29
-------------------------------------------------------------------------------
-- Brief Single-bit half-adder with carry out
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.riscv_pkg.all;
entity shifter_tb is
end shifter_tb;
architecture tb of half_adder_tb is
signal src : std_logic;
signal opcode : std_logic;
signal shamt : std_logic;
signal funct3 : std_logic;
signal out : std_logic;
constant PERIOD : time := 10 ns;
begin
-- DUT
dut: entity work.half_adder
port map (
i_src1 => src;
i_opcode => b;
i_arith => arith;
i_shamt => shamt;
i_funct3 =>funct3;
o_sh => out;
);
-- Main TB process
p_main : process
begin
report "BEGIN SIMULATION";
report "SHIFT";
-- decalage logique à gauche
src1 <= '0100';
opcode <= '0110011';
funct3 <= '001'
shamt<= '1'
wait for PERIOD;
assert out = '0101'
report "Shift error" severity error;
wait for PERIOD;
-- decalage logique à droite
src1 <= '1010';
opcode <= '0110011';
funct3 <= '101'
arith <= '0'
shamt<= '1'
wait for PERIOD;
assert out = '0101'
report "Shift error" severity error;
wait for PERIOD;
-- decalage arithmetique à droite
src1 <= '1010';
opcode <= '0110011';
funct3 <= '101'
arith <= '1'
shamt<= '1'
wait for PERIOD;
assert out = '1101'
report "Shift error" severity error;
wait for PERIOD;
report "SHIFT IMMEDIATE";
-- decalage logique à gauche
src1 <= '0100';
opcode <= '0010011';
funct3 <= '001'
shamt<= '1'
wait for PERIOD;
assert out = '0101'
report "Shift error" severity error;
wait for PERIOD;
-- decalage logique à droite
src1 <= '1010';
opcode <= '0010011';
funct3 <= '101'
arith <= '0'
shamt<= '1'
wait for PERIOD;
assert out = '0101'
report "Shift error" severity error;
wait for PERIOD;
-- decalage arithmetique à droite
src1 <= '1010';
opcode <= '0010011';
funct3 <= '101'
arith <= '1'
shamt<= '1'
wait for PERIOD;
assert out = '1101'
report "Shift error" severity error;
wait for PERIOD;
end process p_main;
end architecture tb;