Implémentation BUGGUÉE de l'additionneur, correctifs aux TB

sources/half_adder_tb.vhd

 -------------------------------------------------------------------------------
 -- Project  ELE8304 : Circuits intégrés à très grande échelle
 -------------------------------------------------------------------------------
--- File     half_adder.vhd
+-- File     riscv_adder_tb.vhd
 -- Authors  Titouan Luard <luardtitouan@gmail.com> 
 --          Yann Roberge <yann.roberge@polymtl.ca> 
 -- Lab      GRM - Polytechnique Montreal
--- Date     2021-10-29
+-- Date     2021-11-05
 -------------------------------------------------------------------------------
--- Brief    Single-bit half-adder with carry out
+-- Brief    -bit half-adder with carry out
 -------------------------------------------------------------------------------
 library ieee;
 use ieee.std_logic_1164.all;

sources/riscv_adder.vhd

 -------------------------------------------------------------------------------
 -- Project  ELE8304 : Circuits intégrés à très grande échelle
 -------------------------------------------------------------------------------
--- File     riscv_pkg.vhd
--- Author   Mickael Fiorentino  <mickael.fiorentino@polymtl.ca>
+-- File     riscv_adder.vhd
+-- Authors  Titouan Luard <luardtitouan@gmail.com> 
+--          Yann Roberge <yann.roberge@polymtl.ca> 
 -- Lab      GRM - Polytechnique Montreal
--- Date     2019-08-09
+-- Date     2021-10-29
 -------------------------------------------------------------------------------
--- Brief    Package for constants, components, and procedures
+-- Brief    Full adder, supports sign-extension, addition-subtraction,
+--          signed and unsigned.
 -------------------------------------------------------------------------------
 library ieee;
 use ieee.std_logic_1164.all;
@@ -28,7 +30,88 @@ entity riscv_adder is
 end entity riscv_adder;
 
 architecture beh of riscv_adder is
+  -- Entrées sign-extended
+  signal a_ext      : std_logic_vector(N downto 0);
+  signal b_ext      : std_logic_vector(N downto 0);
 
+  -- Complément à deux de B
+  signal b_compl2   : std_logic_vector(N downto 0);
+
+  -- Version de B à utiliser pour le calcul (complément ou pas)
+  signal b_operand  : std_logic_vector(N downto 0);
+
+  -- Signaux temporaires
+  signal temp_sum1  : std_logic_vector(N downto 0);
+  signal temp_sum2  : std_logic_vector(N-1 downto 0);
+  signal temp_carry1 : std_logic_vector(N downto 0);
+  signal temp_carry2 : std_logic_vector(N-1 downto 0);
+  signal ored_carries : std_logic_vector(N-1 downto 0);
+
+  -- Bits de contrôles
+  constant OP_UNSIGNED : std_logic := '0';  
+  constant OP_SIGNED : std_logic := '1';
+
+  constant OP_ADD : std_logic := '0';  
+  constant OP_SUBTRACT : std_logic := '1';
 begin
   
+  sign_extend:
+  process (all) is
+  begin
+    if (i_sign = OP_UNSIGNED) then
+      a_ext <= '0' & i_a;
+      b_ext <= '0' & i_b;
+    else
+      a_ext <= i_a(N-1) & i_a;
+      b_ext <= i_b(N-1) & i_b;
+    end if;
+  end process sign_extend;
+
+  -- 2's complement
+  b_compl2 <= std_logic_vector( unsigned(not(b_ext)) + 1 );
+  
+  -- Addition ou soustraction
+  b_operand <= b_compl2 when i_sub = OP_SUBTRACT else b_ext;
+  
+  gen_half_adders_top:
+  for i in 0 to N-1 generate
+    half_adder: entity work.half_adder
+      port map (
+        i_a     => a_ext(i),
+        i_b     => b_ext(i),
+        o_sum   => temp_sum1(i),
+        o_carry => temp_carry1(i)
+      );
+  end generate;
+
+  -- Gestion des retenues
+  ored_carries <= temp_carry1(N-1 downto 0) or (temp_carry2(N-2 downto 0) & '0');
+  
+  gen_half_adders_bottom:
+  for i in 0 to N-2 generate
+      half_adder: entity work.half_adder
+        port map (
+          i_a     => ored_carries(i),
+          i_b     => temp_sum1(i+1),
+          o_sum   => temp_sum2(i), --o_sum(2*i - 1);
+          o_carry => temp_carry2(i)
+        );
+  end generate;
+
+  -- Assignation de la somme:
+  -- Les bits d'index pairs viennent des half-adder du haut
+  -- Les bits d'index impairs viennent des half-adders du bas
+  sum_out:
+  process (all) is
+  begin
+    for i in 0 to N loop
+      if (i mod 2 = 0) then
+        o_sum(i) <= temp_sum1(i);
+      else
+        o_sum(i) <= temp_sum2(i-1);
+      end if;
+    end loop;
+  end process sum_out;
+
 end architecture beh;
+

sources/riscv_adder_tb.vhd

+-------------------------------------------------------------------------------
+-- Project  ELE8304 : Circuits intégrés à très grande échelle
+-------------------------------------------------------------------------------
+-- File     riscv_adder_tb.vhd
+-- Authors  Titouan Luard <luardtitouan@gmail.com> 
+--          Yann Roberge <yann.roberge@polymtl.ca> 
+-- Lab      GRM - Polytechnique Montreal
+-- Date     2021-11-05
+-------------------------------------------------------------------------------
+-- Brief    Full adder, supports sign-extension, addition-subtraction,
+--          signed and unsigned.
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+library work;
+use work.riscv_pkg.all;
+
+entity riscv_adder_tb is
+end riscv_adder_tb;
+
+architecture tb of riscv_adder_tb is
+
+    constant N   : positive := 32;
+
+    signal a    : std_logic_vector(N-1 downto 0);
+    signal b    : std_logic_vector(N-1 downto 0);
+    signal sign : std_logic;
+    signal sub  : std_logic;
+    signal sum  : std_logic_vector(N downto 0);
+
+    constant PERIOD   : time := 1250 ps;
+
+begin
+
+  -- DUT
+  dut: entity work.riscv_adder
+    generic map (
+      N => N
+    )
+    port map (
+      i_a    => a,
+      i_b    => b,
+      i_sign => sign,
+      i_sub  => sub,
+      o_sum  => sum
+    );
+
+  -- Main TB process
+  p_main : process
+  begin
+    -- Vecteurs de tests
+
+    report "BEGIN SIMULATION";
+    a <= std_logic_vector(to_unsigned(12345, a'length));
+    b <= std_logic_vector(to_unsigned(2345,  b'length));
+    sign <= '0';
+    sub <= '0';
+    wait for PERIOD;
+    assert sum = std_logic_vector(to_unsigned(12345 + 2345, sum'length));
+      report "sum error" severity error;
+    wait for PERIOD;
+
+    wait;
+  end process p_main;
+
+end architecture tb;
+