Début de l'étage EXECUTE

sources/riscv_decode.vhd

@@ -262,7 +262,6 @@ begin
     end case; 
   end process decode_jump_decode;
 
---------------------------------------
   --signal shamt  : std_logic_vector(SHAMT_WIDTH-1 downto 0);
   decode_shamt:
   process (opcode, funct3) is
@@ -353,7 +352,13 @@ begin
         arith <= '0';
         sign <= SIGN_UNSIGNED;
 
-      -- B,U,LUI,J,R-TYPEs
+      when OPCODE_BEQ =>
+        -- BEQ: Subtract src1 and src2, take branch if zero
+        alu_opcode <= ALUOP_ADD;
+        arith <= ARITH_SUBTRACT;
+        sign <= SIGN_UNSIGNED;
+
+      -- U,LUI,J,R-TYPEs
       -- Unsupported instructions
       when others =>
         alu_opcode <= (others => '0');
@@ -371,6 +376,8 @@ begin
   begin
     if rising_edge(i_clk) then
       if i_rstn = '1' and i_flush = '0' then
+        o_decode_reg.opcode <= opcode;
+
         o_decode_reg.shamt <= shamt;
         o_decode_reg.arith <= arith;
         o_decode_reg.sign  <= sign;
@@ -380,6 +387,8 @@ begin
         o_decode_reg.pc     <= pc;
         o_decode_reg.imm    <= imm;
       else
+        o_decode_reg.opcode <= (others => '0');
+
         o_decode_reg.shamt <= (others => '0');
         o_decode_reg.arith <= '0';
         o_decode_reg.sign  <= '0';

sources/riscv_execute.vhd

+-------------------------------------------------------------------------------
+-- Project  ELE8304 : Circuits intégrés à très grande échelle
+-------------------------------------------------------------------------------
+-- File     riscv_execute.vhd
+-- Authors  Titouan Luard <luardtitouan@gmail.com> 
+--          Yann Roberge <yann.roberge@polymtl.ca> 
+-- Lab      GRM - Polytechnique Montreal
+-- Date     2021-12-04
+-------------------------------------------------------------------------------
+-- Brief    Execute stage of the pipeline
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+
+library work;
+use work.riscv_pkg.all;
+
+entity riscv_execute is
+  port (
+    -- Entrées de l'étage Decode
+    i_decode_reg : in decode_reg;
+
+    -- Sorties
+    o_pc_transfer : out std_logic;
+    o_pc_target   : out std_logic_vector(XLEN-1 downto 0);
+
+    o_flush : out std_logic;
+
+    -- Sorties registrées
+    o_execute_reg : out execute_reg);
+end entity riscv_execute;
+
+architecture beh of riscv_execute is
+
+  signal alu_src2 : std_logic_vector(XLEN-1 downto 0);
+
+  -- Sorties
+  signal alu_result : std_logic_vector(XLEN-1 downto 0);
+  signal store_data : std_logic;
+
+  alias opcode is i_decode_reg.opcode;
+  alias jump   is i_decode_reg.jump;
+  alias branch is i_decode_reg.branch;
+
+  constant ALL_ZEROES : std_logic_vector(XLEN-1 downto 0) := (others => '0');
+begin
+
+  -- PC transfer
+  -- transfert si jump ou si la condition du BEQ est vraie  
+  -- flush la pipeline dans ce même cas
+  -- toute la gestion de conflit se fait ici
+  -- ie. branch prediction
+  pc_transfer:
+  process (jump, branch, alu_result) is
+  begin
+    if jump = '1' or (branch = '1' and alu_result = ALL_ZEROES) then
+      o_flush <= '1';
+      o_pc_transfer <= '1';
+    else
+      o_flush <= '0';
+      o_pc_transfer <= '0';
+    end if;
+  end process pc_transfer;
+
+  -- DEBUG
+  o_pc_target <= (others => '1');
+  o_execute_reg.alu_result <= (others => '1');
+  o_execute_reg.store_data <= '1';
+
+  -- Résolution des opérations arithmétiques et logiques
+  -- TODO: the whole thing is a big mux depending on OPCODE
+
+  -- Ajustement du PC en cas de saut ou branchement
+  -- TODO: same here. big opcode mux
+
+  -- Écriture du registre execute
+  -- TODO: same as decode register write thingy
+
+end architecture beh;

sources/riscv_pkg.vhd

@@ -159,6 +159,8 @@ package riscv_pkg is
 
 
   type decode_reg is record
+    opcode : std_logic_vector(OPCODE_WIDTH downto 0);
+
     alu_opcode : std_logic_vector(ALUOP_WIDTH-1 downto 0);
     shamt : std_logic_vector(SHAMT_WIDTH-1 downto 0);
     arith : std_logic;
@@ -172,8 +174,10 @@ package riscv_pkg is
 
 
   type execute_reg is record
-    -- TODO
-    debug : std_logic;
+    opcode : std_logic_vector(OPCODE_WIDTH downto 0);
+
+    alu_result: std_logic_vector(XLEN-1 downto 0);
+    store_data: std_logic;
   end record execute_reg;