MàJ du fetch

sources/fetch.vhd

@@ -27,47 +27,51 @@ entity fetch is
     i_stall :     in std_logic;
     i_transfert : in std_logic;
     i_target :    in std_logic_vector(XLEN-1 downto 0);
-    i_mem_read :  in std_logic_vector(XLEN-1 downto 0);
     i_flush :     in std_logic;
+    i_mem :       in std_logic_vector(XLEN-1 downto 0);
     
-    o_mem_addr :  out std_logic_vector(7 downto 0));
-    o_if:         out std_logic_vector(XLEN-1 downto 0));
-    
-    
+    o_pc:            out std_logic_vector(9 downto 0);
+    o_fetch:         out std_logic_vector(XLEN-1 downto 0));
 end entity fetch;
 
 architecture beh of fetch is
 
 signal i_fetch : std_logic_vector(XLEN-1 downto 0);
-
+signal temp_pc :std_logic_vector(XLEN-1 downto 0);
 begin
 
 pc: entity work.riscv_pc
-  generic MAP (N => XLEN)
     port MAP (
       i_clk => i_clk,
       i_rstn => i_rstn,
       i_stall => i_stall,
       i_transfert => i_transfert,
       i_target => i_target,
-      o_pc => i_mem_read);
-      
+      o_pc => temp_pc);
+
+o_pc <= temp_pc(9 downto 0);
+
 fetching: 
 process (i_clk, i_rstn) is
   begin
-    if rising_edge(i_clk) then
-      i_fetch <= i_mem_read
+  if i_rstn = '0' then
+    o_pc <= (others=>'0') ;
+  
+  elsif i_rstn= '1' and rising_edge(i_clk) then
+      i_fetch <= i_mem;
       if i_flush = '1' then
-        i_fetch <= std_logic_vector(RESET_VECTOR) 
+        i_fetch <= std_logic_vector(RESET_VECTOR) ;
         if i_stall = '1' then
-          o_if <= o_if;
+          o_fetch <= o_fetch;
         else
-        o_if<=i_fetch;
+        o_fetch <=i_fetch;
         end if;
     else
-        o_if<=i_fetch;   
+        o_fetch <=i_fetch;   
+      end if;
+    else
+    o_fetch <= i_fetch;
     end if;
-    o_if<= i_fetch
 end process fetching;
 
 

sources/fetch_tb.vhd

+-------------------------------------------------------------------------------
+-- Project  ELE8304 : Circuits intégrés à très grande échelle
+-------------------------------------------------------------------------------
+-- File     riscv_pc_tb.vhd
+-- Authors  Titouan Luard <luardtitouan@gmail.com> 
+--          Yann Roberge <yann.roberge@polymtl.ca> 
+-- Lab      GRM - Polytechnique Montreal
+-- Date     2021-11-19
+-------------------------------------------------------------------------------
+-- Brief    Full adder, supports sign-extension, addition-subtraction,
+--          signed and unsigned.
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+library work;
+use work.riscv_pkg.all;
+
+entity riscv_pc_tb is
+end riscv_pc_tb;
+
+architecture tb of riscv_pc_tb is
+
+    constant XLEN   : positive := 32;
+
+    signal target    : std_logic_vector(XLEN-1 downto 0);
+    signal clk       : std_logic;
+    signal stall     : std_logic;
+    signal transfert : std_logic;
+    signal rstn      : std_logic;
+    signal pc        : std_logic_vector(XLEN-1 downto 0);
+    
+    signal expected_result : std_logic_vector(XLEN-1 downto 0);
+    constant PERIOD   : time := 10 ns;
+
+begin
+
+  -- DUT
+  dut: entity work.riscv_pc
+    generic map (
+      RESET_VECTOR => (others => '0')
+    )
+    port map (
+      i_target    => target,
+      i_clk   => clk,
+      i_stall => stall,
+      i_transfert  => transfert,
+      i_rstn  => rstn,
+      o_pc => pc
+    );
+
+  drive_clk : process
+  begin
+    clk <= '0';
+    wait for PERIOD/2;
+    clk <= '1';
+    wait for PERIOD/2;
+  end process drive_clk;
+
+  -- Main TB process
+  p_main : process
+  begin
+    -- Vecteurs de tests
+
+    report "BEGIN SIMULATION";
+
+    report "initialisation";
+    rstn <= '0' ;
+    expected_result<=(others => '0');
+    wait for PERIOD;
+    assert pc = expected_result
+      report "init error" severity error;
+    wait for PERIOD;
+
+    report "pasage dans l'adder";
+    rstn <= '1';
+    wait for PERIOD; 
+    transfert<= '0';
+    expected_result<=(2 downto 0 => "100",others => '0');
+    assert pc = expected_result
+      report "adder error" severity error;
+    wait for PERIOD;
+
+    report "target";
+    transfert <= '1';
+    target <= (0 downto 0 =>'1', others => '0' );
+    expected_result<=(0 downto 0 =>'1', others => '0');
+    assert pc =  expected_result
+      report "target error" severity error;
+    wait for PERIOD;
+    report "reset";
+    rstn <= '0' ;
+    expected_result<=(others => '0');
+    wait for PERIOD;
+    assert pc = expected_result
+      report "reset error" severity error;
+    wait for PERIOD;
+
+    report "SIMULATION DONE";
+    wait;
+  end process p_main;
+
+end architecture tb;
+

sources/riscv_pc.vhd

@@ -27,7 +27,7 @@ entity riscv_pc is
     i_stall :     in std_logic;
     i_transfert : in std_logic;
     i_target :    in std_logic_vector(XLEN-1 downto 0);
-    o_pc :        out std_logic_vector(XLEN-1 downto 0));
+    o_pc :        out std_logic_vector(9 downto 0));
 end entity riscv_pc;