Correctifs à l'additionneur

sources/riscv_adder.vhd

@@ -20,7 +20,7 @@ use work.riscv_pkg.all;
 
 entity riscv_adder is
   generic (
-    N : positive);
+    N : positive := 32);
   port (
     i_a    : in  std_logic_vector(N-1 downto 0);
     i_b    : in  std_logic_vector(N-1 downto 0);
@@ -54,7 +54,7 @@ architecture beh of riscv_adder is
   constant OP_ADD : std_logic := '0';  
   constant OP_SUBTRACT : std_logic := '1';
 begin
-  
+
   sign_extend:
   process (all) is
   begin
@@ -74,11 +74,11 @@ begin
   b_operand <= b_compl2 when i_sub = OP_SUBTRACT else b_ext;
   
   gen_half_adders_top:
-  for i in 0 to N-1 generate
+  for i in 0 to N generate
     half_adder: entity work.half_adder
       port map (
         i_a     => a_ext(i),
-        i_b     => b_ext(i),
+        i_b     => b_operand(i),
         o_sum   => temp_sum1(i),
         o_carry => temp_carry1(i)
       );
@@ -86,9 +86,9 @@ begin
 
   -- Gestion des retenues
   ored_carries <= temp_carry1(N-1 downto 0) or (temp_carry2(N-2 downto 0) & '0');
-  
+
   gen_half_adders_bottom:
-  for i in 0 to N-2 generate
+  for i in 0 to N-1 generate
       half_adder: entity work.half_adder
         port map (
           i_a     => ored_carries(i),
@@ -99,19 +99,9 @@ begin
   end generate;
 
   -- Assignation de la somme:
-  -- Les bits d'index pairs viennent des half-adder du haut
-  -- Les bits d'index impairs viennent des half-adders du bas
-  sum_out:
-  process (all) is
-  begin
-    for i in 0 to N loop
-      if (i mod 2 = 0) then
-        o_sum(i) <= temp_sum1(i);
-      else
-        o_sum(i) <= temp_sum2(i-1);
-      end if;
-    end loop;
-  end process sum_out;
+  -- Le LSB vient des half-adders du haut
+  -- Le reste vient des half-adders du bas
+  o_sum <= temp_sum2 & temp_sum1(0);
 
 end architecture beh;