TB de l'additionneur complété (mais pas exhaustif)

sources/riscv_adder_tb.vhd

@@ -31,7 +31,7 @@ architecture tb of riscv_adder_tb is
     signal sub  : std_logic;
     signal sum  : std_logic_vector(N downto 0);
 
-    constant PERIOD   : time := 1250 ps;
+    constant PERIOD   : time := 10 ns;
 
 begin
 
@@ -54,15 +54,48 @@ begin
     -- Vecteurs de tests
 
     report "BEGIN SIMULATION";
+
+    report "Unsigned addition";
     a <= std_logic_vector(to_unsigned(12345, a'length));
     b <= std_logic_vector(to_unsigned(2345,  b'length));
     sign <= '0';
     sub <= '0';
     wait for PERIOD;
-    assert sum = std_logic_vector(to_unsigned(12345 + 2345, sum'length));
-      report "sum error" severity error;
+    assert sum = std_logic_vector(to_unsigned(12345 + 2345, sum'length))
+      report "unsigned addition error" severity error;
+    wait for PERIOD;
+
+    report "Signed addition";
+    a <= std_logic_vector(to_signed(12345, a'length));
+    b <= std_logic_vector(to_signed(-2346, b'length));
+    sign <= '1';
+    sub <= '0';
+    wait for PERIOD;
+    assert sum = std_logic_vector(to_signed(12345 - 2346, sum'length))
+      report "signed addition error" severity error;
+    wait for PERIOD;
+
+    report "Unsigned subtraction";
+    a <= std_logic_vector(to_unsigned(12345, a'length));
+    b <= std_logic_vector(to_unsigned(2346, b'length));
+    sign <= '0';
+    sub <= '1';
+    wait for PERIOD;
+    assert sum = std_logic_vector(to_unsigned(12345 - 2346, sum'length))
+      report "signed addition error" severity error;
+    wait for PERIOD;
+
+    report "Signed subtraction";
+    a <= std_logic_vector(to_signed(12345, a'length));
+    b <= std_logic_vector(to_signed(-2346, b'length));
+    sign <= '1';
+    sub <= '1';
+    wait for PERIOD;
+    assert sum = std_logic_vector(to_signed(12345 + 2346, sum'length))
+      report "signed addition error" severity error;
     wait for PERIOD;
 
+    report "SIMULATION DONE";
     wait;
   end process p_main;