riscv_core_tb.vhd

-------------------------------------------------------------------------------
-- Project  ELE8304 : Circuits intégrés à très grande échelle
-------------------------------------------------------------------------------
-- File     riscv_rf_tb.vhd
-- Authors  Titouan Luard <luardtitouan@gmail.com> 
--          Yann Roberge <yann.roberge@polymtl.ca> 
-- Lab      ELE8304-9
-- Date     2021-12-03
-------------------------------------------------------------------------------
-- Brief    RISC-V core testbench
--          Very broche-à-foin but fully functional testbench
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;

library work;
use work.riscv_pkg.all;

entity riscv_core_tb is
end riscv_core_tb;

architecture tb of riscv_core_tb is

  signal dmem_addr : std_logic_vector(DMEM_ADDR_WIDTH downto 0);
  signal dmem_en   : std_logic;
  signal dmem_read : std_logic_vector(XLEN-1 downto 0);

  signal dmem_we    : std_logic;
  signal dmem_write : std_logic_vector(XLEN-1 downto 0);

  signal imem_addr : std_logic_vector(IMEM_ADDR_WIDTH downto 0);
  signal imem_en   : std_logic;
  signal imem_read : std_logic_vector(XLEN-1 downto 0);

  signal clk : std_logic;
  signal rstn : std_logic;

  signal imem_addr_lsb : std_logic_vector(IMEM_ADDR_WIDTH+1 downto 0);
  signal dmem_addr_lsb : std_logic_vector(DMEM_ADDR_WIDTH+1 downto 0);

  -- Entrées/Sorties du DUT
  constant PERIOD : time := 10 ns;

begin

  -- Instanciation du DUT
  dut: entity work.riscv_core
    port map (
      o_dmem_addr => dmem_addr_lsb,
      o_dmem_en   => dmem_en,
      i_dmem_read => dmem_read,

      o_dmem_we    => dmem_we,
      o_dmem_write => dmem_write,

      o_imem_addr => imem_addr_lsb,
      o_imem_en   => imem_en,
      i_imem_read => imem_read,

      i_clk   => clk,
      i_rstn  => rstn
    );

  imem_addr <= "0" & imem_addr_lsb(IMEM_ADDR_WIDTH+1 downto 2);
  dmem_addr <= "1" & dmem_addr_lsb(DMEM_ADDR_WIDTH+1 downto 2);

  -- Instanciation de la mémoire
  main_memory: entity work.dpm
    generic map (
      WIDTH => 32,
      DEPTH => 11,
      RESET => 16#00000000#,
      INIT  => "memory.mem")
    port map (
      -- Port A INSTRUCTION  ---- ROM
      i_a_clk   => clk,            -- Clock
      i_a_rstn  => rstn,           -- Reset Address
      i_a_en    => imem_en,            -- Port enable
      i_a_we    => '0',            -- Write enable
      i_a_addr  => imem_addr,      -- Address port
      i_a_write => (others => '0'),   -- Data write port
      o_a_read  => imem_read,      -- Data read port

      -- Port B DATA
      i_b_clk   => clk,            -- Clock
      i_b_rstn  => rstn,           -- Reset Address
      i_b_en    => dmem_en,             -- Port enable
      i_b_we    => dmem_we,             -- Write enable
      i_b_addr  => dmem_addr,      -- Address port
      i_b_write => dmem_write,     -- Data write port
      o_b_read  => dmem_read       -- Data read port
    );

  -- Drive clock
  drive_clk : process is
  begin
    clk <= '0';
    wait for PERIOD/2;
    clk <= '1';
    wait for PERIOD/2;
  end process drive_clk;

  -- Main TB process
  p_main : process is
  begin
    rstn <= '0';
    wait for 2*PERIOD; 
    rstn <= '1';
    wait for PERIOD; 

    -- Body intentionally left blank

    wait for 1000*PERIOD; 

    report "NON-SELF-CHECKING TB, CHECK THE WAVEFORM MANUALLY";
    wait;

  end process p_main;

end architecture tb;