riscv_core.vhd

-------------------------------------------------------------------------------
-- Project  ELE8304 : Circuits intégrés à très grande échelle
-------------------------------------------------------------------------------
-- File     riscv_core.vhd
-- Authors  Titouan Luard <luardtitouan@gmail.com> 
--          Yann Roberge <yann.roberge@polymtl.ca> 
-- Lab      ELE8304-9
-- Date     2021-12-03
-------------------------------------------------------------------------------
-- Brief    RISC-V processor entire pipeline
--          We had to cut some corner because the project is way too big
--          Pls give us the marks
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;

library work;
use work.riscv_pkg.all;

entity riscv_core is
  port (
    -- Interface telle que définie figure 12
    o_dmem_addr : out std_logic_vector(DMEM_ADDR_WIDTH+1 downto 0);
    o_dmem_en   : out std_logic;
    i_dmem_read : in  std_logic_vector(XLEN-1 downto 0);

    o_dmem_we    : out std_logic;
    o_dmem_write : out std_logic_vector(XLEN-1 downto 0);

    o_imem_addr : out std_logic_vector(IMEM_ADDR_WIDTH+1 downto 0);
    o_imem_en   : out std_logic;
    i_imem_read : in  std_logic_vector(XLEN-1 downto 0);

    -- Divers
    i_clk  : in std_logic;
    i_rstn : in std_logic
  );
end entity riscv_core;


architecture beh of riscv_core is

  -- Registres entre les étages de pipeline
  signal fetch_reg      : fetch_reg;
  signal decode_reg     : decode_reg;
  signal execute_reg    : execute_reg;
  signal memory_reg     : memory_reg;
  signal write_back_reg : write_back_reg;

  -- Signaux non_registrés entre les étages
  signal rs1_data  : std_logic_vector(XLEN-1 downto 0);
  signal rs2_data  : std_logic_vector(XLEN-1 downto 0);
  signal dmem_read : std_logic_vector(XLEN-1 downto 0);

  -- Signaux de contrôle
  signal stall        : std_logic;
  signal pc_transfer  : std_logic;
  signal flush        : std_logic;
  signal pc_target    : std_logic_vector(XLEN-1 downto 0);

begin

  -- Étage Fetch
  fetch_inst: entity work.fetch
    generic map (
      RESET_VECTOR => std_logic_vector(to_unsigned(4*(16#00000009#), XLEN))
    )
    port map (
      -- Entrées externes au pipeline
      i_clk       => i_clk,
      i_rstn      => i_rstn,

      -- Entrées provenant de l'étage Execute
      i_stall     => stall,
      i_transfert => pc_transfer,
      i_target    => pc_target,
      i_flush     => flush,

      -- Interface vers la mémoire d'instruction
      i_mem_read  => i_imem_read,
      o_mem_addr  => o_imem_addr,

      -- Sorties
      o_fetch_reg => fetch_reg
    );

  -- Étage Decode
  decode_inst: entity work.riscv_decode
    port map (
      -- Entrées provenant de l'étage FETCH
      i_fetch_reg => fetch_reg,

      -- Entrées provenant de l'étage WRITE-BACK
      i_write_back_reg => write_back_reg,

      -- Entrée provenant de l'étage EXECUTE
      i_flush => flush,

      -- Entrées externes au pipeline
      i_rstn => i_rstn,
      i_clk  => i_clk,

      -- Sorties
      o_rs1_data => rs1_data,
      o_rs2_data => rs2_data,

      o_decode_reg => decode_reg
    );

  -- Étage Execute
  execute_inst: entity work.riscv_execute
    port map (
      -- Entrées de l'étage Decode
      i_decode_reg => decode_reg,

      i_rs1_data => rs1_data,
      i_rs2_data => rs2_data,

      -- Entrées de l'étage Write Back (forwarding)
      i_write_back_reg => write_back_reg,

      -- Sorties
      o_pc_transfer => pc_transfer,
      o_pc_target   => pc_target,

      o_flush => flush,
      o_stall => stall,

      -- Entrées externes au pipeline
      i_rstn => i_rstn,
      i_clk  => i_clk,

      -- Sorties registrées
      o_execute_reg => execute_reg
    );

  -- Étage Memory Access
  memory_access_inst: entity work.memory_access
    port map (
      -- Entrées provenant de l'extérieur du pipeline
      i_clk        => i_clk,
      i_rstn       => i_rstn,
  
      -- Entrées provenant de l'étage Execute
      i_execute_reg => execute_reg,
  
      -- Sorties
      o_memory_reg => memory_reg,
      o_dmem_read  => dmem_read,
  
      -- Communication avec la DPM
      i_dmem_read  => i_dmem_read,
      o_dmem_addr  => o_dmem_addr,
      o_dmem_write => o_dmem_write,
      o_dmem_we    => o_dmem_we,
      o_dmem_en    => o_dmem_en
    );

  -- Étage Write-Back
  wb_inst: entity work.wb
    port map (
      -- Entrées provenant de l'étage Memory Access
      i_dmem_read  => dmem_read,
      i_alu_result => memory_reg.alu_result,
      i_opcode     => memory_reg.opcode,
      i_rd_addr    => memory_reg.rd_addr,  

      -- Sorties
      o_write_back => write_back_reg
      --o_rd_data => write_back_reg.wr_data,
      --o_rd_addr => write_back_reg.wr_addr,
      --o_we => write_back_reg.we
    );

  o_imem_en <= i_rstn;

  -- DEBUG
  --o_dmem_addr <= (others => '1');
  --o_dmem_en   <= not i_rstn;

  --o_dmem_we    <= '1';
  --o_dmem_write <= (others => '1');

  ----o_imem_addr  <= (others => '1');

end architecture beh;