half_adder.vhd

-------------------------------------------------------------------------------
-- Project  ELE8304 : Circuits intégrés à très grande échelle
-------------------------------------------------------------------------------
-- File     half_adder.vhd
-- Authors  Titouan Luard <luardtitouan@gmail.com> 
--          Yann Roberge <yann.roberge@polymtl.ca> 
-- Lab      GRM - Polytechnique Montreal
-- Date     2021-10-29
-------------------------------------------------------------------------------
-- Brief    Single-bit half-adder with carry out
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

--library work;
--use work.riscv_pkg.all;

entity half_adder is
  port (
    i_a     : in  std_logic;
    i_b     : in  std_logic;
    
    o_sum   : out std_logic;
    o_carry : out std_logic
  );
end entity half_adder;

architecture beh of half_adder is
begin
  o_sum <= i_a xor i_b;
  o_carry <= i_a and i_b;
end architecture beh;