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-------------------------------------------------------------------------------
-- Project ELE8304 : Circuits intégrés à très grande échelle
-------------------------------------------------------------------------------
-- File riscv_adder_tb.vhd
-- Authors Titouan Luard <luardtitouan@gmail.com>
-- Yann Roberge <yann.roberge@polymtl.ca>
-- Lab GRM - Polytechnique Montreal
-------------------------------------------------------------------------------
-- Brief -bit half-adder with carry out
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-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.riscv_pkg.all;
entity half_adder_tb is
end half_adder_tb;
architecture tb of half_adder_tb is
signal a : std_logic;-- := '0';
signal b : std_logic;-- := '0';
signal sum : std_logic;
signal carry : std_logic;
constant PERIOD : time := 1250 ps;
begin
-- DUT
dut: entity work.half_adder
port map (
i_a => a,
i_b => b,
o_carry => carry,
o_sum => sum);
-- Main TB process
p_main : process
begin
report "BEGIN SIMULATION";
a <= '0';
b <= '0';
wait for PERIOD;
assert carry = '0'
report "carry error" severity error;
assert sum = '0'
report "sum error" severity error;
wait for PERIOD;
a <= '0';
b <= '1';
wait for PERIOD;
assert carry = '0'
report "carry error" severity error;
assert sum = '1'
report "sum error" severity error;
wait for PERIOD;
a <= '1';
b <= '0';
wait for PERIOD;
assert carry = '0'
report "carry error" severity error;
assert sum = '1'
report "sum error" severity error;
wait for PERIOD;
a <= '1';
b <= '1';
wait for PERIOD;
assert carry = '1'
report "carry error" severity error;
assert sum = '0'
report "sum error" severity error;
wait for PERIOD;
wait;
end process p_main;
end architecture tb;