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-------------------------------------------------------------------------------
-- Project ELE8304 : Circuits intégrés à très grande échelle
-------------------------------------------------------------------------------
-- File riscv_adder_tb.vhd
-- Authors Titouan Luard <luardtitouan@gmail.com>
-- Yann Roberge <yann.roberge@polymtl.ca>
-- Lab GRM - Polytechnique Montreal
-- Date 2021-11-05
-------------------------------------------------------------------------------
-- Brief Full adder, supports sign-extension, addition-subtraction,
-- signed and unsigned.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.riscv_pkg.all;
entity riscv_adder_tb is
end riscv_adder_tb;
architecture tb of riscv_adder_tb is
constant N : positive := 32;
signal a : std_logic_vector(N-1 downto 0);
signal b : std_logic_vector(N-1 downto 0);
signal sign : std_logic;
signal sub : std_logic;
signal sum : std_logic_vector(N downto 0);
constant PERIOD : time := 1250 ps;
begin
-- DUT
dut: entity work.riscv_adder
generic map (
N => N
)
port map (
i_a => a,
i_b => b,
i_sign => sign,
i_sub => sub,
o_sum => sum
);
-- Main TB process
p_main : process
begin
-- Vecteurs de tests
report "BEGIN SIMULATION";
a <= std_logic_vector(to_unsigned(12345, a'length));
b <= std_logic_vector(to_unsigned(2345, b'length));
sign <= '0';
sub <= '0';
wait for PERIOD;
assert sum = std_logic_vector(to_unsigned(12345 + 2345, sum'length));
report "sum error" severity error;
wait for PERIOD;
wait;
end process p_main;
end architecture tb;