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-------------------------------------------------------------------------------
-- Project ELE8304 : Circuits intégrés à très grande échelle
-------------------------------------------------------------------------------
-- File riscv_rf_tb.vhd
-- Authors Titouan Luard <luardtitouan@gmail.com>
-- Yann Roberge <yann.roberge@polymtl.ca>
-- Lab ELE8304-9
-- Date 2021-11-19
-------------------------------------------------------------------------------
-- Brief RISC-V Register file
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.riscv_pkg.all;
entity riscv_rf_tb is
end riscv_rf_tb;
architecture tb of riscv_rf_tb is
-- Entrées/Sorties du DUT
--TODO
signal clk : std_logic;
signal rstn : std_logic;
signal we : std_logic_vector;
signal addr_ra : std_logic;
signal data_ra : std_logic;
signal addr_rb : std_logic;
signal data_rb : std_logic;
signal addr_w : std_logic;
signal data_w : std_logic;
-- Procédure pour un vecteur de test
--TODO
procedure test_vector (
constant test_arith : in std_logic;
constant test_sign : in std_logic;
constant test_opcode : in std_logic_vector(ALUOP_WIDTH-1 downto 0);
constant test_shamt : in std_logic_vector(SHAMT_WIDTH-1 downto 0);
constant test_src1 : in std_logic_vector(XLEN-1 downto 0);
constant test_src2 : in std_logic_vector(XLEN-1 downto 0);
signal arith : out std_logic;
signal sign : out std_logic;
signal opcode : out std_logic_vector(ALUOP_WIDTH-1 downto 0);
signal shamt : out std_logic_vector(SHAMT_WIDTH-1 downto 0);
signal src1 : out std_logic_vector(XLEN-1 downto 0);
signal src2 : out std_logic_vector(XLEN-1 downto 0);
signal res : in std_logic_vector(XLEN-1 downto 0);
constant expected_result: in std_logic_vector(XLEN-1 downto 0);
constant period : in time) is
begin
arith <= test_arith;
sign <= test_sign;
opcode <= test_opcode;
shamt <= test_shamt;
src1 <= test_src1;
src2 <= test_src2;
wait for period;
assert res = expected_result
report "RESULT DIFFERS FROM EXPECTED" severity error;
wait for period;
end procedure test_vector;
constant PERIOD : time := 10 ns;
begin
-- Instanciation du DUT
dut: entity work.riscv_rf
port map (
i_clk => clk,
i_rstn => rstn,
i_we => we,
i_addr_ra => addr_ra,
o_data_ra => data_ra,
i_addr_rb => addr_rb,
o_data_rb => data_rb,
i_addr_w => addr_w,
i_data_w => data_w
);
-- Main TB process
--TODO
p_main : process
begin
-- Tests des cas représentatif
report "BEGIN SIMULATION";
-- Write all registers
report "Write"
test_vector (
test_arith => SHIFT_LOGIC,
test_sign => '-',
test_opcode => ALUOP_SH_LEFT,
test_shamt => std_logic_vector(to_unsigned(2, shamt'length)),
test_src1 => (others => '1'),
test_src2 => (others => '-'),
arith => arith,
sign => sign,
opcode => opcode,
shamt => shamt,
src1 => src1,
src2 => src2,
res => res,
expected_result => (1 downto 0 => "00", others => '1'),
period => PERIOD
);
-- Read back all registers
-- Read & Write all registers at the same time
-- Reset file
-- Read all registers
report "SIMULATION DONE";
wait;
end process p_main;
end architecture tb;