Temp

sources_1/imports/rtl/msa_tp1_ex2.vhd

@@ -14,8 +14,8 @@ entity msa_tp1_ex2 is
     Port(
         clk_i : in  STD_LOGIC;
         rst_i : in  STD_LOGIC;
-        bouton_left_i : in  STD_LOGIC;
         bouton_up_i : in  STD_LOGIC;
+        bouton_left_i : in  STD_LOGIC;
         bouton_center_i : in  STD_LOGIC;
         bouton_right_i : in STD_LOGIC;
         bouton_down_i : in STD_LOGIC;
@@ -25,7 +25,15 @@ end msa_tp1_ex2;
 
 architecture Behavioral of msa_tp1_ex2 is
 
-type etat is (); --dclaration des noms d'tats  complter
+type etat is (  start,
+                up_transition,
+                up,
+                left_transition,
+                center_transition,
+                left_center_transition,
+                left_center,
+                final
+                ); --d�claration des noms d'�tats � compl�ter
 signal etat_p, etat_f : etat; --registre d'état
 signal dels_p, dels_f : std_logic_vector(7 downto 0); --registre de sortie
 signal boutons : std_logic_vector(4 downto 0);
@@ -35,10 +43,11 @@ begin
 boutons <= bouton_up_i & bouton_left_i & bouton_center_i & bouton_right_i & bouton_down_i; --mapping de signaux internes à des ports
 dels_o <= dels_p;
 
-P_sync: process( --à compléter)
+P_sync: process(rst_i, clk_i, boutons)
 begin
  if(rst_i = '1')then
-	 --à compléter
+	 etat_p <= start;
+	 dels_p <= 0;
  elsif(clk_i'event and clk_i = '1')then
 	 --à compléter
  end if;