From e47764b0c22942cd358d07d9efd88219dc6603ac Mon Sep 17 00:00:00 2001
From: "mickael@pcys" <mickael.fiorentino@polymtl.ca>
Date: Wed, 9 Oct 2019 15:42:04 -0400
Subject: [PATCH] Nettoyage de la branche master
---
constraints/compteur.syn.sdc | 35 -
implementation/pnr/cds.lib | 2 -
implementation/pnr/netlist/compteur.cts.sdf | 375 -----------
implementation/pnr/netlist/compteur.cts.v | 123 ----
implementation/pnr/netlist/compteur.place.sdf | 287 --------
implementation/pnr/netlist/compteur.place.v | 99 ---
implementation/pnr/netlist/compteur.route.sdf | 375 -----------
implementation/pnr/netlist/compteur.route.v | 123 ----
implementation/pnr/reports/compteur.con.rpt | 18 -
implementation/pnr/reports/compteur.drc.rpt | 11 -
implementation/pnr/reports/compteur.dyn.rpt | 86 ---
implementation/pnr/reports/compteur.stat.rpt | 83 ---
.../pnr/reports/compteur.timing.rpt | 34 -
.../reports/timing/compteur_postCTS.cap.gz | Bin 448 -> 0 bytes
.../reports/timing/compteur_postCTS.fanout.gz | Bin 325 -> 0 bytes
.../reports/timing/compteur_postCTS.length.gz | Bin 240 -> 0 bytes
.../timing/compteur_postCTS.summary.gz | Bin 549 -> 0 bytes
.../reports/timing/compteur_postCTS.tran.gz | Bin 497 -> 0 bytes
.../timing/compteur_postCTS_all.tarpt.gz | Bin 4537 -> 0 bytes
.../timing/compteur_postCTS_default.tarpt.gz | Bin 2775 -> 0 bytes
.../timing/compteur_postCTS_reg2reg.tarpt.gz | Bin 3721 -> 0 bytes
.../compteur_postRoute.SI_Glitches.rpt.gz | Bin 90 -> 0 bytes
.../reports/timing/compteur_postRoute.cap.gz | Bin 450 -> 0 bytes
.../timing/compteur_postRoute.fanout.gz | Bin 326 -> 0 bytes
.../timing/compteur_postRoute.length.gz | Bin 241 -> 0 bytes
.../timing/compteur_postRoute.summary.gz | Bin 566 -> 0 bytes
.../reports/timing/compteur_postRoute.tran.gz | Bin 499 -> 0 bytes
.../timing/compteur_postRoute_all.tarpt.gz | Bin 4711 -> 0 bytes
.../compteur_postRoute_default.tarpt.gz | Bin 2806 -> 0 bytes
.../compteur_postRoute_reg2reg.tarpt.gz | Bin 3892 -> 0 bytes
.../timing/compteur_prePlace.summary.gz | Bin 395 -> 0 bytes
.../timing/compteur_prePlace_all.tarpt.gz | Bin 3932 -> 0 bytes
.../timing/compteur_prePlace_default.tarpt.gz | Bin 2523 -> 0 bytes
.../timing/compteur_prePlace_reg2reg.tarpt.gz | Bin 3220 -> 0 bytes
implementation/syn/netlist/compteur.elab.v | 154 -----
implementation/syn/netlist/compteur.syn.sdf | 323 ---------
implementation/syn/netlist/compteur.syn.v | 44 --
implementation/syn/reports/compteur.check.rpt | 615 ------------------
implementation/syn/reports/compteur.clk.rpt | 45 --
.../syn/reports/compteur.gen.area.rpt | 12 -
.../syn/reports/compteur.gen.gates.rpt | 19 -
.../syn/reports/compteur.gen.power.rpt | 14 -
.../syn/reports/compteur.gen.timing.rpt | 47 --
.../syn/reports/compteur.hier_elab.rpt | 17 -
.../syn/reports/compteur.map.area.rpt | 12 -
.../syn/reports/compteur.map.gates.rpt | 40 --
.../syn/reports/compteur.map.power.rpt | 14 -
.../syn/reports/compteur.map.timing.rpt | 43 --
.../syn/reports/compteur.syn.area.rpt | 12 -
.../syn/reports/compteur.syn.gates.rpt | 40 --
.../syn/reports/compteur.syn.power.rpt | 14 -
.../syn/reports/compteur.syn.timing.rpt | 43 --
.../syn/reports/compteur.timing_lint.rpt | 48 --
scripts/pnr.tcl | 220 -------
scripts/pwr.tcl | 107 ---
scripts/sim.tcl | 91 ---
scripts/syn.tcl | 142 ----
simulation/run.do | 23 -
58 files changed, 3790 deletions(-)
delete mode 100644 constraints/compteur.syn.sdc
delete mode 100644 implementation/pnr/cds.lib
delete mode 100644 implementation/pnr/netlist/compteur.cts.sdf
delete mode 100644 implementation/pnr/netlist/compteur.cts.v
delete mode 100644 implementation/pnr/netlist/compteur.place.sdf
delete mode 100644 implementation/pnr/netlist/compteur.place.v
delete mode 100644 implementation/pnr/netlist/compteur.route.sdf
delete mode 100644 implementation/pnr/netlist/compteur.route.v
delete mode 100644 implementation/pnr/reports/compteur.con.rpt
delete mode 100644 implementation/pnr/reports/compteur.drc.rpt
delete mode 100644 implementation/pnr/reports/compteur.dyn.rpt
delete mode 100644 implementation/pnr/reports/compteur.stat.rpt
delete mode 100644 implementation/pnr/reports/compteur.timing.rpt
delete mode 100644 implementation/pnr/reports/timing/compteur_postCTS.cap.gz
delete mode 100644 implementation/pnr/reports/timing/compteur_postCTS.fanout.gz
delete mode 100644 implementation/pnr/reports/timing/compteur_postCTS.length.gz
delete mode 100644 implementation/pnr/reports/timing/compteur_postCTS.summary.gz
delete mode 100644 implementation/pnr/reports/timing/compteur_postCTS.tran.gz
delete mode 100644 implementation/pnr/reports/timing/compteur_postCTS_all.tarpt.gz
delete mode 100644 implementation/pnr/reports/timing/compteur_postCTS_default.tarpt.gz
delete mode 100644 implementation/pnr/reports/timing/compteur_postCTS_reg2reg.tarpt.gz
delete mode 100644 implementation/pnr/reports/timing/compteur_postRoute.SI_Glitches.rpt.gz
delete mode 100644 implementation/pnr/reports/timing/compteur_postRoute.cap.gz
delete mode 100644 implementation/pnr/reports/timing/compteur_postRoute.fanout.gz
delete mode 100644 implementation/pnr/reports/timing/compteur_postRoute.length.gz
delete mode 100644 implementation/pnr/reports/timing/compteur_postRoute.summary.gz
delete mode 100644 implementation/pnr/reports/timing/compteur_postRoute.tran.gz
delete mode 100644 implementation/pnr/reports/timing/compteur_postRoute_all.tarpt.gz
delete mode 100644 implementation/pnr/reports/timing/compteur_postRoute_default.tarpt.gz
delete mode 100644 implementation/pnr/reports/timing/compteur_postRoute_reg2reg.tarpt.gz
delete mode 100644 implementation/pnr/reports/timing/compteur_prePlace.summary.gz
delete mode 100644 implementation/pnr/reports/timing/compteur_prePlace_all.tarpt.gz
delete mode 100644 implementation/pnr/reports/timing/compteur_prePlace_default.tarpt.gz
delete mode 100644 implementation/pnr/reports/timing/compteur_prePlace_reg2reg.tarpt.gz
delete mode 100644 implementation/syn/netlist/compteur.elab.v
delete mode 100644 implementation/syn/netlist/compteur.syn.sdf
delete mode 100644 implementation/syn/netlist/compteur.syn.v
delete mode 100644 implementation/syn/reports/compteur.check.rpt
delete mode 100644 implementation/syn/reports/compteur.clk.rpt
delete mode 100644 implementation/syn/reports/compteur.gen.area.rpt
delete mode 100644 implementation/syn/reports/compteur.gen.gates.rpt
delete mode 100644 implementation/syn/reports/compteur.gen.power.rpt
delete mode 100644 implementation/syn/reports/compteur.gen.timing.rpt
delete mode 100644 implementation/syn/reports/compteur.hier_elab.rpt
delete mode 100644 implementation/syn/reports/compteur.map.area.rpt
delete mode 100644 implementation/syn/reports/compteur.map.gates.rpt
delete mode 100644 implementation/syn/reports/compteur.map.power.rpt
delete mode 100644 implementation/syn/reports/compteur.map.timing.rpt
delete mode 100644 implementation/syn/reports/compteur.syn.area.rpt
delete mode 100644 implementation/syn/reports/compteur.syn.gates.rpt
delete mode 100644 implementation/syn/reports/compteur.syn.power.rpt
delete mode 100644 implementation/syn/reports/compteur.syn.timing.rpt
delete mode 100644 implementation/syn/reports/compteur.timing_lint.rpt
delete mode 100644 scripts/pnr.tcl
delete mode 100644 scripts/pwr.tcl
delete mode 100644 scripts/sim.tcl
delete mode 100644 scripts/syn.tcl
delete mode 100644 simulation/run.do
diff --git a/constraints/compteur.syn.sdc b/constraints/compteur.syn.sdc
deleted file mode 100644
index a6ccf1e..0000000
--- a/constraints/compteur.syn.sdc
+++ /dev/null
@@ -1,35 +0,0 @@
-# ####################################################################
-
-# Created by Genus(TM) Synthesis Solution 18.10-p003_1 on Tue Oct 08 12:54:55 EDT 2019
-
-# ####################################################################
-
-set sdc_version 2.0
-
-set_units -capacitance 1000.0fF
-set_units -time 1000.0ps
-
-# Set the current design
-current_design compteur
-
-create_clock -name "clk" -period 1.25 -waveform {0.0 0.625} [get_ports i_clk]
-set_load -pin_load -max 0.5 [get_ports {o_cnt[3]}]
-set_load -pin_load -max 0.5 [get_ports {o_cnt[2]}]
-set_load -pin_load -max 0.5 [get_ports {o_cnt[1]}]
-set_load -pin_load -max 0.5 [get_ports {o_cnt[0]}]
-set_false_path -from [get_ports i_rstn]
-set_clock_gating_check -setup 0.0
-set_input_delay -clock [get_clocks clk] -add_delay 0.2 [get_ports i_clk]
-set_input_delay -clock [get_clocks clk] -add_delay 0.2 [get_ports i_rstn]
-set_input_delay -clock [get_clocks clk] -add_delay 0.2 [get_ports i_en]
-set_output_delay -clock [get_clocks clk] -add_delay 0.2 [get_ports {o_cnt[3]}]
-set_output_delay -clock [get_clocks clk] -add_delay 0.2 [get_ports {o_cnt[2]}]
-set_output_delay -clock [get_clocks clk] -add_delay 0.2 [get_ports {o_cnt[1]}]
-set_output_delay -clock [get_clocks clk] -add_delay 0.2 [get_ports {o_cnt[0]}]
-set_driving_cell -lib_cell BUFX20 -library slow_vdd1v0 -pin "Y" [get_ports i_clk]
-set_driving_cell -lib_cell BUFX20 -library slow_vdd1v0 -pin "Y" [get_ports i_rstn]
-set_driving_cell -lib_cell BUFX20 -library slow_vdd1v0 -pin "Y" [get_ports i_en]
-set_ideal_network [get_pins {rstn_sync_reg[1]/Q}]
-set_dont_use [get_lib_cells slow_vdd1v0/HOLDX1]
-set_clock_uncertainty -setup 0.1 [get_clocks clk]
-set_clock_uncertainty -hold 0.03 [get_clocks clk]
diff --git a/implementation/pnr/cds.lib b/implementation/pnr/cds.lib
deleted file mode 100644
index 8a32172..0000000
--- a/implementation/pnr/cds.lib
+++ /dev/null
@@ -1,2 +0,0 @@
-INCLUDE /export/tmp/fiorentino/Projects/tutoriel_numerique/compteur/implementation/cds.lib
-DEFINE compteur_oa compteur_oa
diff --git a/implementation/pnr/netlist/compteur.cts.sdf b/implementation/pnr/netlist/compteur.cts.sdf
deleted file mode 100644
index 054dbd1..0000000
--- a/implementation/pnr/netlist/compteur.cts.sdf
+++ /dev/null
@@ -1,375 +0,0 @@
-(DELAYFILE
- (SDFVERSION "2.1")
- (DESIGN "compteur")
- (DATE "Tue Oct 8 12:57:34 2019")
- (VENDOR "Cadence Design Systems, Inc.")
- (PROGRAM "Innovus")
- (VERSION "v18.10-p002_1 ((64bit) 05/29/2018 19:19 (Linux 2.6.18-194.el5))")
- (DIVIDER /)
- (VOLTAGE 0.900000::0.900000)
- (PROCESS "1.000000::1.000000")
- (TEMPERATURE 125.000000::125.000000)
- (TIMESCALE 1.0 ns)
-
- (CELL
- (CELLTYPE "compteur")
- (INSTANCE)
- (DELAY
- (ABSOLUTE
- (INTERCONNECT cnt_reg\[0\]/Q g345__9682/A1N (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[0\]/Q g347__1309/B (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[0\]/Q FE_OFC26_FE_OFN8_o_cnt_0/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC7_o_cnt_1/Y g342__3772/A0 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC22_FE_OFN5_o_cnt_1/Y FE_OFC7_o_cnt_1/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[1\]/Q g339__4296/B0 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[1\]/Q g344__4547/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[1\]/Q cnt_reg\[1\]/D (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[1\]/Q g343__1474/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[1\]/Q FE_OFC22_FE_OFN5_o_cnt_1/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[1\]/Q FE_OFC23_FE_OFN5_o_cnt_1/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC20_FE_OFN3_o_cnt_2/Y FE_OFC21_FE_OFN3_o_cnt_2/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC20_FE_OFN3_o_cnt_2/Y g337__8780/A1 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC20_FE_OFN3_o_cnt_2/Y g346__2683/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC20_FE_OFN3_o_cnt_2/Y g342__3772/A1 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[2\]/Q cnt_reg\[2\]/SE (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[2\]/Q FE_OFC20_FE_OFN3_o_cnt_2/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC1_o_cnt_3/Y g339__4296/A0 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC24_FE_OFN0_o_cnt_3/Y FE_OFC1_o_cnt_3/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[3\]/Q g337__8780/A0 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[3\]/Q g346__2683/B (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[3\]/Q FE_OFC24_FE_OFN0_o_cnt_3/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[3\]/Q FE_OFC25_FE_OFN0_o_cnt_3/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT rstn_sync_reg\[1\]/Q cnt_reg\[3\]/RN (0.000::0.000) (0.000::0.000))
- (INTERCONNECT rstn_sync_reg\[1\]/Q cnt_reg\[2\]/RN (0.000::0.000) (0.000::0.000))
- (INTERCONNECT rstn_sync_reg\[1\]/Q cnt_reg\[1\]/RN (0.000::0.000) (0.000::0.000))
- (INTERCONNECT rstn_sync_reg\[1\]/Q cnt_reg\[0\]/RN (0.000::0.000) (0.000::0.000))
- (INTERCONNECT rstn_sync_reg\[0\]/Q rstn_sync_reg\[1\]/D (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g347__1309/Y cnt_reg\[1\]/SE (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g347__1309/Y g342__3772/B0 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g347__1309/Y g343__1474/B (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g347__1309/Y g345__9682/B0 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g346__2683/Y g339__4296/B1 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g346__2683/Y g344__4547/B (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g345__9682/Y cnt_reg\[0\]/D (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g344__4547/Y cnt_reg\[1\]/SI (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g342__3772/Y g339__4296/A1 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC27_n_7/Y cnt_reg\[2\]/D (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g343__1474/Y g337__8780/A2 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g343__1474/Y cnt_reg\[2\]/SI (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g343__1474/Y FE_OFC27_n_7/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g339__4296/Y g337__8780/B0 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g337__8780/Y cnt_reg\[3\]/D (0.000::0.000) (0.000::0.000))
- )
- )
- )
-
- (CELL
- (CELLTYPE "INVX1")
- (INSTANCE FE_OFC27_n_7)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.118::0.118) (0.072::0.072))
- )
- )
- )
-
- (CELL
- (CELLTYPE "CLKBUFX20")
- (INSTANCE FE_OFC26_FE_OFN8_o_cnt_0)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.399::0.399) (0.473::0.473))
- )
- )
- )
-
- (CELL
- (CELLTYPE "CLKBUFX20")
- (INSTANCE FE_OFC25_FE_OFN0_o_cnt_3)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.406::0.406) (0.480::0.480))
- )
- )
- )
-
- (CELL
- (CELLTYPE "INVX1")
- (INSTANCE FE_OFC24_FE_OFN0_o_cnt_3)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.070::0.070) (0.072::0.072))
- )
- )
- )
-
- (CELL
- (CELLTYPE "CLKBUFX20")
- (INSTANCE FE_OFC23_FE_OFN5_o_cnt_1)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.423::0.423) (0.497::0.497))
- )
- )
- )
-
- (CELL
- (CELLTYPE "INVX1")
- (INSTANCE FE_OFC22_FE_OFN5_o_cnt_1)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.090::0.090) (0.091::0.091))
- )
- )
- )
-
- (CELL
- (CELLTYPE "CLKINVX20")
- (INSTANCE FE_OFC21_FE_OFN3_o_cnt_2)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.374::0.374) (0.454::0.454))
- )
- )
- )
-
- (CELL
- (CELLTYPE "INVX2")
- (INSTANCE FE_OFC20_FE_OFN3_o_cnt_2)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.094::0.094) (0.100::0.100))
- )
- )
- )
-
- (CELL
- (CELLTYPE "INVX1")
- (INSTANCE FE_OFC7_o_cnt_1)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.041::0.041) (0.044::0.044))
- )
- )
- )
-
- (CELL
- (CELLTYPE "INVX1")
- (INSTANCE FE_OFC1_o_cnt_3)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.035::0.035) (0.037::0.037))
- )
- )
- )
-
- (CELL
- (CELLTYPE "DFFRHQX1")
- (INSTANCE rstn_sync_reg\[1\])
- (DELAY
- (ABSOLUTE
- (IOPATH RN Q () (0.072::0.072))
- (IOPATH CK Q (0.243::0.243) (0.213::0.213))
- )
- )
- (TIMINGCHECK
- (WIDTH (negedge RN) (::0.135))
- (SETUPHOLD (posedge D) (posedge CK) (::0.114) (::-0.067))
- (SETUPHOLD (negedge D) (posedge CK) (::0.047) (::0.025))
- (WIDTH (posedge CK) (::0.152))
- (WIDTH (negedge CK) (::0.165))
- )
- )
-
- (CELL
- (CELLTYPE "DFFRHQX1")
- (INSTANCE rstn_sync_reg\[0\])
- (DELAY
- (ABSOLUTE
- (IOPATH RN Q () (0.080::0.080))
- (IOPATH CK Q (0.250::0.250) (0.222::0.222))
- )
- )
- (TIMINGCHECK
- (WIDTH (negedge RN) (::0.135))
- (SETUPHOLD (posedge D) (posedge CK) (::0.100) (::-0.054))
- (SETUPHOLD (negedge D) (posedge CK) (::0.034) (::0.036))
- (WIDTH (posedge CK) (::0.152))
- (WIDTH (negedge CK) (::0.165))
- )
- )
-
- (CELL
- (CELLTYPE "DFFRHQX1")
- (INSTANCE cnt_reg\[3\])
- (DELAY
- (ABSOLUTE
- (IOPATH RN Q () (0.109::0.109))
- (IOPATH CK Q (0.285::0.285) (0.260::0.260))
- )
- )
- (TIMINGCHECK
- (WIDTH (negedge RN) (::0.081))
- (SETUPHOLD (posedge D) (posedge CK) (::0.154) (::-0.106))
- (SETUPHOLD (negedge D) (posedge CK) (::0.076) (::-0.000))
- (WIDTH (posedge CK) (::0.152))
- (WIDTH (negedge CK) (::0.165))
- )
- )
-
- (CELL
- (CELLTYPE "SDFFRHQX1")
- (INSTANCE cnt_reg\[2\])
- (DELAY
- (ABSOLUTE
- (IOPATH RN Q () (0.087::0.087))
- (IOPATH CK Q (0.265::0.265) (0.238::0.238))
- )
- )
- (TIMINGCHECK
- (WIDTH (negedge RN) (::0.081))
- (SETUPHOLD (posedge SI) (posedge CK) (::0.229) (::-0.168))
- (SETUPHOLD (negedge SI) (posedge CK) (::0.200) (::-0.105))
- (SETUPHOLD (posedge SE) (posedge CK) (::0.186) (::-0.066))
- (SETUPHOLD (negedge SE) (posedge CK) (::0.218) (::-0.026))
- (SETUPHOLD (posedge D) (posedge CK) (::0.210) (::-0.148))
- (SETUPHOLD (negedge D) (posedge CK) (::0.129) (::-0.039))
- (WIDTH (posedge CK) (::0.152))
- (WIDTH (negedge CK) (::0.161))
- )
- )
-
- (CELL
- (CELLTYPE "OAI31X1")
- (INSTANCE g337__8780)
- (DELAY
- (ABSOLUTE
- (IOPATH A0 Y (0.156::0.156) (0.144::0.144))
- (IOPATH A1 Y (0.162::0.162) (0.143::0.143))
- (IOPATH A2 Y (0.167::0.167) (0.112::0.112))
- (IOPATH B0 Y (0.080::0.080) (0.124::0.124))
- )
- )
- )
-
- (CELL
- (CELLTYPE "SDFFRHQX1")
- (INSTANCE cnt_reg\[1\])
- (DELAY
- (ABSOLUTE
- (IOPATH RN Q () (0.129::0.129))
- (IOPATH CK Q (0.303::0.303) (0.279::0.279))
- )
- )
- (TIMINGCHECK
- (WIDTH (negedge RN) (::0.081))
- (SETUPHOLD (posedge SI) (posedge CK) (::0.211) (::-0.150))
- (SETUPHOLD (negedge SI) (posedge CK) (::0.140) (::-0.048))
- (SETUPHOLD (posedge SE) (posedge CK) (::0.195) (::-0.074))
- (SETUPHOLD (negedge SE) (posedge CK) (::0.226) (::-0.033))
- (SETUPHOLD (posedge D) (posedge CK) (::0.248) (::-0.185))
- (SETUPHOLD (negedge D) (posedge CK) (::0.174) (::-0.081))
- (WIDTH (posedge CK) (::0.152))
- (WIDTH (negedge CK) (::0.161))
- )
- )
-
- (CELL
- (CELLTYPE "AOI22X1")
- (INSTANCE g339__4296)
- (DELAY
- (ABSOLUTE
- (IOPATH A0 Y (0.090::0.090) (0.105::0.105))
- (IOPATH A1 Y (0.112::0.112) (0.126::0.126))
- (IOPATH B0 Y (0.127::0.127) (0.125::0.125))
- (IOPATH B1 Y (0.068::0.068) (0.069::0.069))
- )
- )
- )
-
- (CELL
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- (INSTANCE cnt_reg\[0\])
- (DELAY
- (ABSOLUTE
- (IOPATH RN Q () (0.102::0.102))
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- )
- (TIMINGCHECK
- (WIDTH (negedge RN) (::0.081))
- (SETUPHOLD (posedge D) (posedge CK) (::0.128) (::-0.081))
- (SETUPHOLD (negedge D) (posedge CK) (::0.055) (::0.018))
- (WIDTH (posedge CK) (::0.152))
- (WIDTH (negedge CK) (::0.165))
- )
- )
-
- (CELL
- (CELLTYPE "OAI21X1")
- (INSTANCE g342__3772)
- (DELAY
- (ABSOLUTE
- (IOPATH A0 Y (0.075::0.075) (0.090::0.090))
- (IOPATH A1 Y (0.118::0.118) (0.123::0.123))
- (IOPATH B0 Y (0.062::0.062) (0.103::0.103))
- )
- )
- )
-
- (CELL
- (CELLTYPE "NAND2XL")
- (INSTANCE g343__1474)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.128::0.128) (0.194::0.194))
- (IOPATH B Y (0.090::0.090) (0.154::0.154))
- )
- )
- )
-
- (CELL
- (CELLTYPE "NOR2X1")
- (INSTANCE g344__4547)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.113::0.113) (0.101::0.101))
- (IOPATH B Y (0.056::0.056) (0.043::0.043))
- )
- )
- )
-
- (CELL
- (CELLTYPE "AOI2BB1X1")
- (INSTANCE g345__9682)
- (DELAY
- (ABSOLUTE
- (IOPATH A0N Y (0.097::0.097) (0.117::0.117))
- (IOPATH A1N Y (0.112::0.112) (0.131::0.131))
- (IOPATH B0 Y (0.087::0.087) (0.071::0.071))
- )
- )
- )
-
- (CELL
- (CELLTYPE "AND2X1")
- (INSTANCE g346__2683)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.171::0.171) (0.120::0.120))
- (IOPATH B Y (0.171::0.171) (0.112::0.112))
- )
- )
- )
-
- (CELL
- (CELLTYPE "AND2X1")
- (INSTANCE g347__1309)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.148::0.148) (0.094::0.094))
- (IOPATH B Y (0.183::0.183) (0.126::0.126))
- )
- )
- )
-)
diff --git a/implementation/pnr/netlist/compteur.cts.v b/implementation/pnr/netlist/compteur.cts.v
deleted file mode 100644
index 83d0759..0000000
--- a/implementation/pnr/netlist/compteur.cts.v
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
-###############################################################
-# Generated by: Cadence Innovus 18.10-p002_1
-# OS: Linux x86_64(Host ID pcys41)
-# Generated on: Tue Oct 8 12:57:34 2019
-# Design: compteur
-# Command: saveNetlist /export/tmp/fiorentino/Projects/tutoriel_numerique/compteur/implementation/pnr/netlist/compteur.cts.v
-###############################################################
-*/
-// Generated by Cadence Genus(TM) Synthesis Solution 18.10-p003_1
-// Generated on: Oct 8 2019 12:54:55 EDT (Oct 8 2019 16:54:55 UTC)
-// Verification Directory fv/compteur
-module compteur (
- i_clk,
- i_rstn,
- i_en,
- o_cnt);
- input i_clk;
- input i_rstn;
- input i_en;
- output [3:0] o_cnt;
-
- // Internal wires
- wire FE_OFN8_o_cnt_0;
- wire FE_OFN7_o_cnt_1;
- wire FE_OFN6_o_cnt_1;
- wire FE_OFN5_o_cnt_1;
- wire FE_OFN4_o_cnt_2;
- wire FE_OFN3_o_cnt_2;
- wire FE_OFN2_o_cnt_3;
- wire FE_OFN1_o_cnt_3;
- wire FE_OFN0_o_cnt_3;
- wire [1:0] rstn_sync;
- wire n_1;
- wire n_2;
- wire n_3;
- wire n_4;
- wire n_5;
- wire n_6;
- wire n_7;
- wire n_8;
- wire n_9;
-
- INVX1 FE_OFC27_n_7 (.Y(n_6),
- .A(n_7));
- CLKBUFX20 FE_OFC26_FE_OFN8_o_cnt_0 (.Y(o_cnt[0]),
- .A(FE_OFN8_o_cnt_0));
- CLKBUFX20 FE_OFC25_FE_OFN0_o_cnt_3 (.Y(o_cnt[3]),
- .A(FE_OFN0_o_cnt_3));
- INVX1 FE_OFC24_FE_OFN0_o_cnt_3 (.Y(FE_OFN1_o_cnt_3),
- .A(FE_OFN0_o_cnt_3));
- CLKBUFX20 FE_OFC23_FE_OFN5_o_cnt_1 (.Y(o_cnt[1]),
- .A(FE_OFN5_o_cnt_1));
- INVX1 FE_OFC22_FE_OFN5_o_cnt_1 (.Y(FE_OFN6_o_cnt_1),
- .A(FE_OFN5_o_cnt_1));
- CLKINVX20 FE_OFC21_FE_OFN3_o_cnt_2 (.Y(o_cnt[2]),
- .A(FE_OFN4_o_cnt_2));
- INVX2 FE_OFC20_FE_OFN3_o_cnt_2 (.Y(FE_OFN4_o_cnt_2),
- .A(FE_OFN3_o_cnt_2));
- INVX1 FE_OFC7_o_cnt_1 (.Y(FE_OFN7_o_cnt_1),
- .A(FE_OFN6_o_cnt_1));
- INVX1 FE_OFC1_o_cnt_3 (.Y(FE_OFN2_o_cnt_3),
- .A(FE_OFN1_o_cnt_3));
- DFFRHQX1 \rstn_sync_reg[1] (.Q(rstn_sync[1]),
- .D(rstn_sync[0]),
- .RN(i_rstn),
- .CK(i_clk));
- DFFRHQX1 \rstn_sync_reg[0] (.Q(rstn_sync[0]),
- .D(1'b1),
- .RN(i_rstn),
- .CK(i_clk));
- DFFRHQX1 \cnt_reg[3] (.Q(FE_OFN0_o_cnt_3),
- .D(n_9),
- .RN(rstn_sync[1]),
- .CK(i_clk));
- SDFFRHQX1 \cnt_reg[2] (.Q(FE_OFN3_o_cnt_2),
- .D(n_6),
- .SE(FE_OFN3_o_cnt_2),
- .SI(n_7),
- .RN(rstn_sync[1]),
- .CK(i_clk));
- OAI31X1 g337__8780 (.Y(n_9),
- .A0(FE_OFN0_o_cnt_3),
- .A1(FE_OFN4_o_cnt_2),
- .A2(n_7),
- .B0(n_8));
- SDFFRHQX1 \cnt_reg[1] (.Q(FE_OFN5_o_cnt_1),
- .D(FE_OFN5_o_cnt_1),
- .SE(n_1),
- .SI(n_4),
- .RN(rstn_sync[1]),
- .CK(i_clk));
- AOI22X1 g339__4296 (.Y(n_8),
- .A0(FE_OFN2_o_cnt_3),
- .A1(n_5),
- .B0(FE_OFN5_o_cnt_1),
- .B1(n_2));
- DFFRHQX1 \cnt_reg[0] (.Q(FE_OFN8_o_cnt_0),
- .D(n_3),
- .RN(rstn_sync[1]),
- .CK(i_clk));
- OAI21X1 g342__3772 (.Y(n_5),
- .A0(FE_OFN7_o_cnt_1),
- .A1(FE_OFN4_o_cnt_2),
- .B0(n_1));
- NAND2XL g343__1474 (.Y(n_7),
- .A(FE_OFN5_o_cnt_1),
- .B(n_1));
- NOR2X1 g344__4547 (.Y(n_4),
- .A(FE_OFN5_o_cnt_1),
- .B(n_2));
- AOI2BB1X1 g345__9682 (.Y(n_3),
- .A0N(i_en),
- .A1N(FE_OFN8_o_cnt_0),
- .B0(n_1));
- AND2X1 g346__2683 (.Y(n_2),
- .A(FE_OFN4_o_cnt_2),
- .B(FE_OFN0_o_cnt_3));
- AND2X1 g347__1309 (.Y(n_1),
- .A(i_en),
- .B(FE_OFN8_o_cnt_0));
-endmodule
-
diff --git a/implementation/pnr/netlist/compteur.place.sdf b/implementation/pnr/netlist/compteur.place.sdf
deleted file mode 100644
index fb73c3d..0000000
--- a/implementation/pnr/netlist/compteur.place.sdf
+++ /dev/null
@@ -1,287 +0,0 @@
-(DELAYFILE
- (SDFVERSION "2.1")
- (DESIGN "compteur")
- (DATE "Tue Oct 8 12:57:15 2019")
- (VENDOR "Cadence Design Systems, Inc.")
- (PROGRAM "Innovus")
- (VERSION "v18.10-p002_1 ((64bit) 05/29/2018 19:19 (Linux 2.6.18-194.el5))")
- (DIVIDER /)
- (VOLTAGE 0.900000::0.900000)
- (PROCESS "1.000000::1.000000")
- (TEMPERATURE 125.000000::125.000000)
- (TIMESCALE 1.0 ns)
-
- (CELL
- (CELLTYPE "compteur")
- (INSTANCE)
- (DELAY
- (ABSOLUTE
- (INTERCONNECT cnt_reg\[3\]/Q g337__8780/A0 (0.012::0.012) (0.012::0.012))
- (INTERCONNECT cnt_reg\[3\]/Q g339__4296/A0 (0.012::0.012) (0.012::0.012))
- (INTERCONNECT cnt_reg\[3\]/Q g346__2683/B (0.012::0.012) (0.012::0.012))
- (INTERCONNECT cnt_reg\[2\]/Q cnt_reg\[2\]/SE (0.008::0.008) (0.008::0.008))
- (INTERCONNECT cnt_reg\[2\]/Q g348/A (0.013::0.013) (0.013::0.013))
- (INTERCONNECT cnt_reg\[1\]/Q cnt_reg\[1\]/D (0.008::0.008) (0.008::0.008))
- (INTERCONNECT cnt_reg\[1\]/Q g339__4296/B0 (0.014::0.014) (0.014::0.014))
- (INTERCONNECT cnt_reg\[1\]/Q g342__3772/A0 (0.019::0.019) (0.019::0.019))
- (INTERCONNECT cnt_reg\[1\]/Q g343__1474/A (0.020::0.020) (0.020::0.020))
- (INTERCONNECT cnt_reg\[1\]/Q g344__4547/A (0.012::0.012) (0.012::0.012))
- (INTERCONNECT cnt_reg\[0\]/Q g345__9682/A1N (0.003::0.003) (0.003::0.003))
- (INTERCONNECT cnt_reg\[0\]/Q g347__1309/B (0.003::0.003) (0.003::0.003))
- (INTERCONNECT rstn_sync_reg\[1\]/Q cnt_reg\[3\]/RN (0.000::0.000) (0.000::0.000))
- (INTERCONNECT rstn_sync_reg\[1\]/Q cnt_reg\[2\]/RN (0.000::0.000) (0.000::0.000))
- (INTERCONNECT rstn_sync_reg\[1\]/Q cnt_reg\[1\]/RN (0.000::0.000) (0.000::0.000))
- (INTERCONNECT rstn_sync_reg\[1\]/Q cnt_reg\[0\]/RN (0.000::0.000) (0.000::0.000))
- (INTERCONNECT rstn_sync_reg\[0\]/Q rstn_sync_reg\[1\]/D (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g348/Y g337__8780/A1 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g348/Y g342__3772/A1 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g348/Y g346__2683/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g347__1309/Y cnt_reg\[1\]/SE (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g347__1309/Y g342__3772/B0 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g347__1309/Y g343__1474/B (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g347__1309/Y g345__9682/B0 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g346__2683/Y g339__4296/B1 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g346__2683/Y g344__4547/B (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g345__9682/Y cnt_reg\[0\]/D (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g344__4547/Y cnt_reg\[1\]/SI (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g342__3772/Y g339__4296/A1 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g341/Y cnt_reg\[2\]/D (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g343__1474/Y cnt_reg\[2\]/SI (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g343__1474/Y g337__8780/A2 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g343__1474/Y g341/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g339__4296/Y g337__8780/B0 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g337__8780/Y cnt_reg\[3\]/D (0.000::0.000) (0.000::0.000))
- )
- )
- )
-
- (CELL
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- (INSTANCE rstn_sync_reg\[1\])
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- (SETUPHOLD (negedge SI) (posedge CK) (::0.513) (::-0.394))
- (SETUPHOLD (posedge SE) (posedge CK) (::5.252) (::-4.979))
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- )
-
- (CELL
- (CELLTYPE "INVX3")
- (INSTANCE g348)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (6.000::6.000) (5.210::5.210))
- )
- )
- )
-)
diff --git a/implementation/pnr/netlist/compteur.place.v b/implementation/pnr/netlist/compteur.place.v
deleted file mode 100644
index ff5eeeb..0000000
--- a/implementation/pnr/netlist/compteur.place.v
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
-###############################################################
-# Generated by: Cadence Innovus 18.10-p002_1
-# OS: Linux x86_64(Host ID pcys41)
-# Generated on: Tue Oct 8 12:57:15 2019
-# Design: compteur
-# Command: saveNetlist /export/tmp/fiorentino/Projects/tutoriel_numerique/compteur/implementation/pnr/netlist/compteur.place.v
-###############################################################
-*/
-// Generated by Cadence Genus(TM) Synthesis Solution 18.10-p003_1
-// Generated on: Oct 8 2019 12:54:55 EDT (Oct 8 2019 16:54:55 UTC)
-// Verification Directory fv/compteur
-module compteur (
- i_clk,
- i_rstn,
- i_en,
- o_cnt);
- input i_clk;
- input i_rstn;
- input i_en;
- output [3:0] o_cnt;
-
- // Internal wires
- wire [1:0] rstn_sync;
- wire n_0;
- wire n_1;
- wire n_2;
- wire n_3;
- wire n_4;
- wire n_5;
- wire n_6;
- wire n_7;
- wire n_8;
- wire n_9;
-
- DFFRHQX1 \rstn_sync_reg[1] (.Q(rstn_sync[1]),
- .D(rstn_sync[0]),
- .RN(i_rstn),
- .CK(i_clk));
- DFFRHQX1 \rstn_sync_reg[0] (.Q(rstn_sync[0]),
- .D(1'b1),
- .RN(i_rstn),
- .CK(i_clk));
- DFFRHQX1 \cnt_reg[3] (.Q(o_cnt[3]),
- .D(n_9),
- .RN(rstn_sync[1]),
- .CK(i_clk));
- SDFFRHQX1 \cnt_reg[2] (.Q(o_cnt[2]),
- .D(n_6),
- .SE(o_cnt[2]),
- .SI(n_7),
- .RN(rstn_sync[1]),
- .CK(i_clk));
- OAI31X1 g337__8780 (.Y(n_9),
- .A0(o_cnt[3]),
- .A1(n_0),
- .A2(n_7),
- .B0(n_8));
- SDFFRHQX1 \cnt_reg[1] (.Q(o_cnt[1]),
- .D(o_cnt[1]),
- .SE(n_1),
- .SI(n_4),
- .RN(rstn_sync[1]),
- .CK(i_clk));
- AOI22X1 g339__4296 (.Y(n_8),
- .A0(o_cnt[3]),
- .A1(n_5),
- .B0(o_cnt[1]),
- .B1(n_2));
- DFFRHQX1 \cnt_reg[0] (.Q(o_cnt[0]),
- .D(n_3),
- .RN(rstn_sync[1]),
- .CK(i_clk));
- INVX1 g341 (.Y(n_6),
- .A(n_7));
- OAI21X1 g342__3772 (.Y(n_5),
- .A0(o_cnt[1]),
- .A1(n_0),
- .B0(n_1));
- NAND2X1 g343__1474 (.Y(n_7),
- .A(o_cnt[1]),
- .B(n_1));
- NOR2X1 g344__4547 (.Y(n_4),
- .A(o_cnt[1]),
- .B(n_2));
- AOI2BB1X1 g345__9682 (.Y(n_3),
- .A0N(i_en),
- .A1N(o_cnt[0]),
- .B0(n_1));
- AND2X1 g346__2683 (.Y(n_2),
- .A(n_0),
- .B(o_cnt[3]));
- CLKAND2X3 g347__1309 (.Y(n_1),
- .A(i_en),
- .B(o_cnt[0]));
- INVX3 g348 (.Y(n_0),
- .A(o_cnt[2]));
-endmodule
-
diff --git a/implementation/pnr/netlist/compteur.route.sdf b/implementation/pnr/netlist/compteur.route.sdf
deleted file mode 100644
index 999119a..0000000
--- a/implementation/pnr/netlist/compteur.route.sdf
+++ /dev/null
@@ -1,375 +0,0 @@
-(DELAYFILE
- (SDFVERSION "2.1")
- (DESIGN "compteur")
- (DATE "Tue Oct 8 12:58:27 2019")
- (VENDOR "Cadence Design Systems, Inc.")
- (PROGRAM "Innovus")
- (VERSION "v18.10-p002_1 ((64bit) 05/29/2018 19:19 (Linux 2.6.18-194.el5))")
- (DIVIDER /)
- (VOLTAGE 0.900000::0.900000)
- (PROCESS "1.000000::1.000000")
- (TEMPERATURE 125.000000::125.000000)
- (TIMESCALE 1.0 ns)
-
- (CELL
- (CELLTYPE "compteur")
- (INSTANCE)
- (DELAY
- (ABSOLUTE
- (INTERCONNECT cnt_reg\[0\]/Q g345__9682/A1N (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[0\]/Q g347__1309/B (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[0\]/Q FE_OFC26_FE_OFN8_o_cnt_0/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC7_o_cnt_1/Y g342__3772/A0 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC22_FE_OFN5_o_cnt_1/Y FE_OFC7_o_cnt_1/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[1\]/Q g339__4296/B0 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[1\]/Q g344__4547/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[1\]/Q cnt_reg\[1\]/D (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[1\]/Q g343__1474/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[1\]/Q FE_OFC22_FE_OFN5_o_cnt_1/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[1\]/Q FE_OFC23_FE_OFN5_o_cnt_1/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC20_FE_OFN3_o_cnt_2/Y FE_OFC21_FE_OFN3_o_cnt_2/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC20_FE_OFN3_o_cnt_2/Y g337__8780/A1 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC20_FE_OFN3_o_cnt_2/Y g346__2683/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC20_FE_OFN3_o_cnt_2/Y g342__3772/A1 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[2\]/Q cnt_reg\[2\]/SE (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[2\]/Q FE_OFC20_FE_OFN3_o_cnt_2/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC1_o_cnt_3/Y g339__4296/A0 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC24_FE_OFN0_o_cnt_3/Y FE_OFC1_o_cnt_3/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[3\]/Q g337__8780/A0 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[3\]/Q g346__2683/B (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[3\]/Q FE_OFC24_FE_OFN0_o_cnt_3/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[3\]/Q FE_OFC25_FE_OFN0_o_cnt_3/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT rstn_sync_reg\[1\]/Q cnt_reg\[3\]/RN (0.000::0.000) (0.000::0.000))
- (INTERCONNECT rstn_sync_reg\[1\]/Q cnt_reg\[2\]/RN (0.000::0.000) (0.000::0.000))
- (INTERCONNECT rstn_sync_reg\[1\]/Q cnt_reg\[1\]/RN (0.000::0.000) (0.000::0.000))
- (INTERCONNECT rstn_sync_reg\[1\]/Q cnt_reg\[0\]/RN (0.000::0.000) (0.000::0.000))
- (INTERCONNECT rstn_sync_reg\[0\]/Q rstn_sync_reg\[1\]/D (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g347__1309/Y cnt_reg\[1\]/SE (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g347__1309/Y g342__3772/B0 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g347__1309/Y g343__1474/B (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g347__1309/Y g345__9682/B0 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g346__2683/Y g339__4296/B1 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g346__2683/Y g344__4547/B (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g345__9682/Y cnt_reg\[0\]/D (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g344__4547/Y cnt_reg\[1\]/SI (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g342__3772/Y g339__4296/A1 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC27_n_7/Y cnt_reg\[2\]/D (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g343__1474/Y g337__8780/A2 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g343__1474/Y cnt_reg\[2\]/SI (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g343__1474/Y FE_OFC27_n_7/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g339__4296/Y g337__8780/B0 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g337__8780/Y cnt_reg\[3\]/D (0.000::0.000) (0.000::0.000))
- )
- )
- )
-
- (CELL
- (CELLTYPE "INVX1")
- (INSTANCE FE_OFC27_n_7)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.127::0.127) (0.077::0.077))
- )
- )
- )
-
- (CELL
- (CELLTYPE "CLKBUFX20")
- (INSTANCE FE_OFC26_FE_OFN8_o_cnt_0)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.408::0.408) (0.480::0.480))
- )
- )
- )
-
- (CELL
- (CELLTYPE "CLKBUFX20")
- (INSTANCE FE_OFC25_FE_OFN0_o_cnt_3)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.415::0.415) (0.487::0.487))
- )
- )
- )
-
- (CELL
- (CELLTYPE "INVX1")
- (INSTANCE FE_OFC24_FE_OFN0_o_cnt_3)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.071::0.071) (0.073::0.073))
- )
- )
- )
-
- (CELL
- (CELLTYPE "CLKBUFX20")
- (INSTANCE FE_OFC23_FE_OFN5_o_cnt_1)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.424::0.424) (0.498::0.498))
- )
- )
- )
-
- (CELL
- (CELLTYPE "INVX1")
- (INSTANCE FE_OFC22_FE_OFN5_o_cnt_1)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.092::0.092) (0.093::0.093))
- )
- )
- )
-
- (CELL
- (CELLTYPE "CLKINVX20")
- (INSTANCE FE_OFC21_FE_OFN3_o_cnt_2)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.380::0.380) (0.459::0.459))
- )
- )
- )
-
- (CELL
- (CELLTYPE "INVX2")
- (INSTANCE FE_OFC20_FE_OFN3_o_cnt_2)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.095::0.095) (0.102::0.102))
- )
- )
- )
-
- (CELL
- (CELLTYPE "INVX1")
- (INSTANCE FE_OFC7_o_cnt_1)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.042::0.042) (0.044::0.044))
- )
- )
- )
-
- (CELL
- (CELLTYPE "INVX1")
- (INSTANCE FE_OFC1_o_cnt_3)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.036::0.036) (0.038::0.038))
- )
- )
- )
-
- (CELL
- (CELLTYPE "DFFRHQX1")
- (INSTANCE rstn_sync_reg\[1\])
- (DELAY
- (ABSOLUTE
- (IOPATH RN Q () (0.072::0.072))
- (IOPATH CK Q (0.242::0.242) (0.213::0.213))
- )
- )
- (TIMINGCHECK
- (WIDTH (negedge RN) (0.135::0.135))
- (SETUPHOLD (posedge D) (posedge CK) (0.113::0.113) (-0.067::-0.067))
- (SETUPHOLD (negedge D) (posedge CK) (0.046::0.046) (0.026::0.026))
- (WIDTH (posedge CK) (0.152::0.152))
- (WIDTH (negedge CK) (0.165::0.165))
- )
- )
-
- (CELL
- (CELLTYPE "DFFRHQX1")
- (INSTANCE rstn_sync_reg\[0\])
- (DELAY
- (ABSOLUTE
- (IOPATH RN Q () (0.079::0.079))
- (IOPATH CK Q (0.249::0.249) (0.221::0.221))
- )
- )
- (TIMINGCHECK
- (WIDTH (negedge RN) (0.135::0.135))
- (SETUPHOLD (posedge D) (posedge CK) (0.100::0.100) (-0.054::-0.054))
- (SETUPHOLD (negedge D) (posedge CK) (0.034::0.034) (0.036::0.036))
- (WIDTH (posedge CK) (0.152::0.152))
- (WIDTH (negedge CK) (0.165::0.165))
- )
- )
-
- (CELL
- (CELLTYPE "DFFRHQX1")
- (INSTANCE cnt_reg\[3\])
- (DELAY
- (ABSOLUTE
- (IOPATH RN Q () (0.111::0.111))
- (IOPATH CK Q (0.286::0.286) (0.261::0.261))
- )
- )
- (TIMINGCHECK
- (WIDTH (negedge RN) (0.081::0.081))
- (SETUPHOLD (posedge D) (posedge CK) (0.157::0.157) (-0.073::-0.073))
- (SETUPHOLD (negedge D) (posedge CK) (0.078::0.078) (0.009::0.009))
- (WIDTH (posedge CK) (0.152::0.152))
- (WIDTH (negedge CK) (0.165::0.165))
- )
- )
-
- (CELL
- (CELLTYPE "SDFFRHQX1")
- (INSTANCE cnt_reg\[2\])
- (DELAY
- (ABSOLUTE
- (IOPATH RN Q () (0.088::0.088))
- (IOPATH CK Q (0.266::0.266) (0.239::0.239))
- )
- )
- (TIMINGCHECK
- (WIDTH (negedge RN) (0.081::0.081))
- (SETUPHOLD (posedge SI) (posedge CK) (0.233::0.233) (-0.164::-0.164))
- (SETUPHOLD (negedge SI) (posedge CK) (0.208::0.208) (-0.110::-0.110))
- (SETUPHOLD (posedge SE) (posedge CK) (0.187::0.187) (-0.066::-0.066))
- (SETUPHOLD (negedge SE) (posedge CK) (0.218::0.218) (-0.026::-0.026))
- (SETUPHOLD (posedge D) (posedge CK) (0.211::0.211) (-0.149::-0.149))
- (SETUPHOLD (negedge D) (posedge CK) (0.130::0.130) (-0.038::-0.038))
- (WIDTH (posedge CK) (0.152::0.152))
- (WIDTH (negedge CK) (0.161::0.161))
- )
- )
-
- (CELL
- (CELLTYPE "OAI31X1")
- (INSTANCE g337__8780)
- (DELAY
- (ABSOLUTE
- (IOPATH A0 Y (0.159::0.159) (0.146::0.146))
- (IOPATH A1 Y (0.165::0.165) (0.146::0.146))
- (IOPATH A2 Y (0.177::0.177) (0.117::0.117))
- (IOPATH B0 Y (0.080::0.080) (0.125::0.125))
- )
- )
- )
-
- (CELL
- (CELLTYPE "SDFFRHQX1")
- (INSTANCE cnt_reg\[1\])
- (DELAY
- (ABSOLUTE
- (IOPATH RN Q () (0.131::0.131))
- (IOPATH CK Q (0.305::0.305) (0.281::0.281))
- )
- )
- (TIMINGCHECK
- (WIDTH (negedge RN) (0.081::0.081))
- (SETUPHOLD (posedge SI) (posedge CK) (0.210::0.210) (-0.147::-0.147))
- (SETUPHOLD (negedge SI) (posedge CK) (0.140::0.140) (-0.038::-0.038))
- (SETUPHOLD (posedge SE) (posedge CK) (0.196::0.196) (-0.074::-0.074))
- (SETUPHOLD (negedge SE) (posedge CK) (0.227::0.227) (-0.032::-0.032))
- (SETUPHOLD (posedge D) (posedge CK) (0.249::0.249) (-0.184::-0.184))
- (SETUPHOLD (negedge D) (posedge CK) (0.176::0.176) (-0.080::-0.080))
- (WIDTH (posedge CK) (0.152::0.152))
- (WIDTH (negedge CK) (0.161::0.161))
- )
- )
-
- (CELL
- (CELLTYPE "AOI22X1")
- (INSTANCE g339__4296)
- (DELAY
- (ABSOLUTE
- (IOPATH A0 Y (0.090::0.090) (0.105::0.105))
- (IOPATH A1 Y (0.113::0.113) (0.127::0.127))
- (IOPATH B0 Y (0.129::0.129) (0.126::0.126))
- (IOPATH B1 Y (0.068::0.068) (0.069::0.069))
- )
- )
- )
-
- (CELL
- (CELLTYPE "DFFRHQX1")
- (INSTANCE cnt_reg\[0\])
- (DELAY
- (ABSOLUTE
- (IOPATH RN Q () (0.103::0.103))
- (IOPATH CK Q (0.279::0.279) (0.253::0.253))
- )
- )
- (TIMINGCHECK
- (WIDTH (negedge RN) (0.081::0.081))
- (SETUPHOLD (posedge D) (posedge CK) (0.128::0.128) (-0.079::-0.079))
- (SETUPHOLD (negedge D) (posedge CK) (0.055::0.055) (0.023::0.023))
- (WIDTH (posedge CK) (0.152::0.152))
- (WIDTH (negedge CK) (0.165::0.165))
- )
- )
-
- (CELL
- (CELLTYPE "OAI21X1")
- (INSTANCE g342__3772)
- (DELAY
- (ABSOLUTE
- (IOPATH A0 Y (0.076::0.076) (0.091::0.091))
- (IOPATH A1 Y (0.120::0.120) (0.125::0.125))
- (IOPATH B0 Y (0.063::0.063) (0.105::0.105))
- )
- )
- )
-
- (CELL
- (CELLTYPE "NAND2XL")
- (INSTANCE g343__1474)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.133::0.133) (0.205::0.205))
- (IOPATH B Y (0.094::0.094) (0.164::0.164))
- )
- )
- )
-
- (CELL
- (CELLTYPE "NOR2X1")
- (INSTANCE g344__4547)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.114::0.114) (0.102::0.102))
- (IOPATH B Y (0.055::0.055) (0.042::0.042))
- )
- )
- )
-
- (CELL
- (CELLTYPE "AOI2BB1X1")
- (INSTANCE g345__9682)
- (DELAY
- (ABSOLUTE
- (IOPATH A0N Y (0.096::0.096) (0.117::0.117))
- (IOPATH A1N Y (0.112::0.112) (0.131::0.131))
- (IOPATH B0 Y (0.087::0.087) (0.071::0.071))
- )
- )
- )
-
- (CELL
- (CELLTYPE "AND2X1")
- (INSTANCE g346__2683)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.172::0.172) (0.121::0.121))
- (IOPATH B Y (0.172::0.172) (0.113::0.113))
- )
- )
- )
-
- (CELL
- (CELLTYPE "AND2X1")
- (INSTANCE g347__1309)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.149::0.149) (0.095::0.095))
- (IOPATH B Y (0.184::0.184) (0.128::0.128))
- )
- )
- )
-)
diff --git a/implementation/pnr/netlist/compteur.route.v b/implementation/pnr/netlist/compteur.route.v
deleted file mode 100644
index a847397..0000000
--- a/implementation/pnr/netlist/compteur.route.v
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
-###############################################################
-# Generated by: Cadence Innovus 18.10-p002_1
-# OS: Linux x86_64(Host ID pcys41)
-# Generated on: Tue Oct 8 12:58:26 2019
-# Design: compteur
-# Command: saveNetlist /export/tmp/fiorentino/Projects/tutoriel_numerique/compteur/implementation/pnr/netlist/compteur.route.v
-###############################################################
-*/
-// Generated by Cadence Genus(TM) Synthesis Solution 18.10-p003_1
-// Generated on: Oct 8 2019 12:54:55 EDT (Oct 8 2019 16:54:55 UTC)
-// Verification Directory fv/compteur
-module compteur (
- i_clk,
- i_rstn,
- i_en,
- o_cnt);
- input i_clk;
- input i_rstn;
- input i_en;
- output [3:0] o_cnt;
-
- // Internal wires
- wire FE_OFN8_o_cnt_0;
- wire FE_OFN7_o_cnt_1;
- wire FE_OFN6_o_cnt_1;
- wire FE_OFN5_o_cnt_1;
- wire FE_OFN4_o_cnt_2;
- wire FE_OFN3_o_cnt_2;
- wire FE_OFN2_o_cnt_3;
- wire FE_OFN1_o_cnt_3;
- wire FE_OFN0_o_cnt_3;
- wire [1:0] rstn_sync;
- wire n_1;
- wire n_2;
- wire n_3;
- wire n_4;
- wire n_5;
- wire n_6;
- wire n_7;
- wire n_8;
- wire n_9;
-
- INVX1 FE_OFC27_n_7 (.Y(n_6),
- .A(n_7));
- CLKBUFX20 FE_OFC26_FE_OFN8_o_cnt_0 (.Y(o_cnt[0]),
- .A(FE_OFN8_o_cnt_0));
- CLKBUFX20 FE_OFC25_FE_OFN0_o_cnt_3 (.Y(o_cnt[3]),
- .A(FE_OFN0_o_cnt_3));
- INVX1 FE_OFC24_FE_OFN0_o_cnt_3 (.Y(FE_OFN1_o_cnt_3),
- .A(FE_OFN0_o_cnt_3));
- CLKBUFX20 FE_OFC23_FE_OFN5_o_cnt_1 (.Y(o_cnt[1]),
- .A(FE_OFN5_o_cnt_1));
- INVX1 FE_OFC22_FE_OFN5_o_cnt_1 (.Y(FE_OFN6_o_cnt_1),
- .A(FE_OFN5_o_cnt_1));
- CLKINVX20 FE_OFC21_FE_OFN3_o_cnt_2 (.Y(o_cnt[2]),
- .A(FE_OFN4_o_cnt_2));
- INVX2 FE_OFC20_FE_OFN3_o_cnt_2 (.Y(FE_OFN4_o_cnt_2),
- .A(FE_OFN3_o_cnt_2));
- INVX1 FE_OFC7_o_cnt_1 (.Y(FE_OFN7_o_cnt_1),
- .A(FE_OFN6_o_cnt_1));
- INVX1 FE_OFC1_o_cnt_3 (.Y(FE_OFN2_o_cnt_3),
- .A(FE_OFN1_o_cnt_3));
- DFFRHQX1 \rstn_sync_reg[1] (.Q(rstn_sync[1]),
- .D(rstn_sync[0]),
- .RN(i_rstn),
- .CK(i_clk));
- DFFRHQX1 \rstn_sync_reg[0] (.Q(rstn_sync[0]),
- .D(1'b1),
- .RN(i_rstn),
- .CK(i_clk));
- DFFRHQX1 \cnt_reg[3] (.Q(FE_OFN0_o_cnt_3),
- .D(n_9),
- .RN(rstn_sync[1]),
- .CK(i_clk));
- SDFFRHQX1 \cnt_reg[2] (.Q(FE_OFN3_o_cnt_2),
- .D(n_6),
- .SE(FE_OFN3_o_cnt_2),
- .SI(n_7),
- .RN(rstn_sync[1]),
- .CK(i_clk));
- OAI31X1 g337__8780 (.Y(n_9),
- .A0(FE_OFN0_o_cnt_3),
- .A1(FE_OFN4_o_cnt_2),
- .A2(n_7),
- .B0(n_8));
- SDFFRHQX1 \cnt_reg[1] (.Q(FE_OFN5_o_cnt_1),
- .D(FE_OFN5_o_cnt_1),
- .SE(n_1),
- .SI(n_4),
- .RN(rstn_sync[1]),
- .CK(i_clk));
- AOI22X1 g339__4296 (.Y(n_8),
- .A0(FE_OFN2_o_cnt_3),
- .A1(n_5),
- .B0(FE_OFN5_o_cnt_1),
- .B1(n_2));
- DFFRHQX1 \cnt_reg[0] (.Q(FE_OFN8_o_cnt_0),
- .D(n_3),
- .RN(rstn_sync[1]),
- .CK(i_clk));
- OAI21X1 g342__3772 (.Y(n_5),
- .A0(FE_OFN7_o_cnt_1),
- .A1(FE_OFN4_o_cnt_2),
- .B0(n_1));
- NAND2XL g343__1474 (.Y(n_7),
- .A(FE_OFN5_o_cnt_1),
- .B(n_1));
- NOR2X1 g344__4547 (.Y(n_4),
- .A(FE_OFN5_o_cnt_1),
- .B(n_2));
- AOI2BB1X1 g345__9682 (.Y(n_3),
- .A0N(i_en),
- .A1N(FE_OFN8_o_cnt_0),
- .B0(n_1));
- AND2X1 g346__2683 (.Y(n_2),
- .A(FE_OFN4_o_cnt_2),
- .B(FE_OFN0_o_cnt_3));
- AND2X1 g347__1309 (.Y(n_1),
- .A(i_en),
- .B(FE_OFN8_o_cnt_0));
-endmodule
-
diff --git a/implementation/pnr/reports/compteur.con.rpt b/implementation/pnr/reports/compteur.con.rpt
deleted file mode 100644
index 94a6f07..0000000
--- a/implementation/pnr/reports/compteur.con.rpt
+++ /dev/null
@@ -1,18 +0,0 @@
-###############################################################
-# Generated by: Cadence Innovus 18.10-p002_1
-# OS: Linux x86_64(Host ID pcys41)
-# Generated on: Tue Oct 8 12:58:26 2019
-# Design: compteur
-# Command: verifyConnectivity -type all -error 1000 -warning 50 -report /export/tmp/fiorentino/Projects/tutoriel_numerique/compteur/implementation/pnr/reports/compteur.con.rpt
-###############################################################
-Verify Connectivity Report is created on Tue Oct 8 12:58:26 2019
-
-
-
-Net VSS: dangling Wire at (16.300, 1.140) (16.300, 1.140) on layer: Metal1
-Net VSS: dangling Wire at (16.300, 11.400) (16.300, 11.400) on layer: Metal1
-
-Begin Summary
- 2 Problem(s) (IMPVFC-94): The net has dangling wire(s).
- 2 total info(s) created.
-End Summary
diff --git a/implementation/pnr/reports/compteur.drc.rpt b/implementation/pnr/reports/compteur.drc.rpt
deleted file mode 100644
index 90d4955..0000000
--- a/implementation/pnr/reports/compteur.drc.rpt
+++ /dev/null
@@ -1,11 +0,0 @@
-###############################################################
-# Generated by: Cadence Innovus 18.10-p002_1
-# OS: Linux x86_64(Host ID pcys41)
-# Generated on: Tue Oct 8 12:58:26 2019
-# Design: compteur
-# Command: verify_drc
-###############################################################
-#set_verify_drc_mode -report /export/tmp/fiorentino/Projects/tutoriel_numerique/compteur/implementation/pnr/reports/compteur.drc.rpt
-
-No DRC violations were found
-
diff --git a/implementation/pnr/reports/compteur.dyn.rpt b/implementation/pnr/reports/compteur.dyn.rpt
deleted file mode 100644
index 72e06bc..0000000
--- a/implementation/pnr/reports/compteur.dyn.rpt
+++ /dev/null
@@ -1,86 +0,0 @@
-*----------------------------------------------------------------------------------------
-* Voltus Power Analysis - Power Calculator - Version v16.16-s020_1 64-bit (05/03/2017 02:27:51)
-* Copyright 2007, Cadence Design Systems, Inc.
-*
-* Date & Time: 2019-Oct-08 13:02:14 (2019-Oct-08 17:02:14 GMT)
-*
-*----------------------------------------------------------------------------------------
-*
-* Design: compteur
-*
-* Liberty Libraries used:
-* /CMC/kits/GPDK45/gsclib045/gsclib045/timing/slow_vdd1v0_basicCells.lib
-*
-* Power Domain used:
-* Rail: VDD Voltage: 0.9
-*
-* DEF Files used:
-* /tmp/ssv_tmpdir_26627_p5AEVU/eps_out_26627.def.gz
-*
-* Switching Activity File used:
-* /export/tmp/fiorentino/Projects/tutoriel_numerique/compteur/simulation/pnr/compteur.vcd
-* Vcd Window used(Start Time, Stop Time): (0,54.375)
-* Vcd Scale Factor: 1
-* * Design annotation coverage: 27/27 = 100%
-*
-* Hierarchical Global Activity: N.A.
-*
-* Global Activity: N.A.
-*
-* Sequential Element Activity: N.A.
-*
-* Primary Input Activity: 0.200000
-*
-* Default icg ratio: N.A.
-*
-* Global Comb ClockGate Ratio: N.A.
-*
-* Power Units = 1mW
-*
-* Time Units = 1e-09 secs
-*
-* report_power -output /export/tmp/fiorentino/Projects/tutoriel_numerique/compteur/implementation/pnr/reports/power -format detailed -report_prefix compteur.dyn
-*
------------------------------------------------------------------------------------------
-
-
-Total Power
------------------------------------------------------------------------------------------
-Total Internal Power: 0.02796512 12.0684%
-Total Switching Power: 0.20375353 87.9300%
-Total Leakage Power: 0.00000367 0.0016%
-Total Power: 0.23172233
------------------------------------------------------------------------------------------
-
-
-Group Internal Switching Leakage Total Percentage
- Power Power Power Power (%)
------------------------------------------------------------------------------------------
-Sequential 0.01725 0.001124 8.766e-07 0.01837 7.928
-Macro 0 0 0 0 0
-IO 0 0 0 0 0
-Combinational 0.01072 0.2026 2.793e-06 0.2134 92.07
-Clock (Combinational) 0 0 0 0 0
-Clock (Sequential) 0 0 0 0 0
------------------------------------------------------------------------------------------
-Total 0.02797 0.2038 3.669e-06 0.2317 100
------------------------------------------------------------------------------------------
-
-
-Rail Voltage Internal Switching Leakage Total Percentage
- Power Power Power Power (%)
------------------------------------------------------------------------------------------
-VDD 0.9 0 0 0 0 0
-
-
------------------------------------------------------------------------------------------
-* Power Distribution Summary:
-* Highest Average Power: FE_OFC26_FE_OFN8_o_cnt_0 (CLKBUFX20): 0.1113
-* Highest Leakage Power: FE_OFC25_FE_OFN0_o_cnt_3 (CLKBUFX20): 6.246e-07
-* Total Cap: 2.03147e-12 F
-* Total instances in design: 24
-* Total instances in design with no power: 0
-* Total instances in design with no activity: 0
-* Total Fillers and Decap: 0
------------------------------------------------------------------------------------------
-
diff --git a/implementation/pnr/reports/compteur.stat.rpt b/implementation/pnr/reports/compteur.stat.rpt
deleted file mode 100644
index 29e4426..0000000
--- a/implementation/pnr/reports/compteur.stat.rpt
+++ /dev/null
@@ -1,83 +0,0 @@
-*----------------------------------------------------------------------------------------
-* Voltus IC Power Integrity Solution 16.16-s051_1 (64bit) 05/16/2017 12:06 (Linux 2.6.18-194.el5)
-*
-*
-* Date & Time: 2019-Oct-08 13:03:48 (2019-Oct-08 17:03:48 GMT)
-*
-*----------------------------------------------------------------------------------------
-*
-* Design: compteur
-*
-* Liberty Libraries used:
-* slow_av: /CMC/kits/GPDK45/gsclib045/gsclib045/timing/slow_vdd1v0_basicCells.lib
-*
-* Power Domain used:
-* Rail: VDD Voltage: 0.9
-*
-* Power View : slow_av
-*
-* User-Defined Activity : N.A.
-*
-* Activity File: N.A.
-*
-* Hierarchical Global Activity: N.A.
-*
-* Global Activity: N.A.
-*
-* Sequential Element Activity: N.A.
-*
-* Primary Input Activity: 0.200000
-*
-* Default icg ratio: N.A.
-*
-* Global Comb ClockGate Ratio: N.A.
-*
-* Power Units = 1mW
-*
-* Time Units = 1e-09 secs
-*
-* report_power -output /export/tmp/fiorentino/Projects/tutoriel_numerique/compteur/implementation/pnr/reports/power -report_prefix compteur.stat -format detailed
-*
------------------------------------------------------------------------------------------
-
-
-Total Power
------------------------------------------------------------------------------------------
-Total Internal Power: 0.02651278 12.1526%
-Total Switching Power: 0.19164970 87.8458%
-Total Leakage Power: 0.00000367 0.0017%
-Total Power: 0.21816615
------------------------------------------------------------------------------------------
-
-
-Group Internal Switching Leakage Total Percentage
- Power Power Power Power (%)
------------------------------------------------------------------------------------------
-Sequential 0.01681 0.001026 9.016e-07 0.01783 8.174
-Macro 0 0 0 0 0
-IO 0 0 0 0 0
-Combinational 0.009707 0.1906 2.772e-06 0.2003 91.83
-Clock (Combinational) 0 0 0 0 0
-Clock (Sequential) 0 0 0 0 0
------------------------------------------------------------------------------------------
-Total 0.02651 0.1916 3.674e-06 0.2182 100
------------------------------------------------------------------------------------------
-
-
-Rail Voltage Internal Switching Leakage Total Percentage
- Power Power Power Power (%)
------------------------------------------------------------------------------------------
-VDD 0.9 0.02651 0.1916 3.674e-06 0.2182 100
-
-
------------------------------------------------------------------------------------------
-* Power Distribution Summary:
-* Highest Average Power: FE_OFC23_FE_OFN5_o_cnt_1 (CLKBUFX20): 0.06309
-* Highest Leakage Power: FE_OFC23_FE_OFN5_o_cnt_1 (CLKBUFX20): 6.197e-07
-* Total Cap: 2.02968e-12 F
-* Total instances in design: 24
-* Total instances in design with no power: 0
-* Total instances in design with no activity: 0
-* Total Fillers and Decap: 0
------------------------------------------------------------------------------------------
-
diff --git a/implementation/pnr/reports/compteur.timing.rpt b/implementation/pnr/reports/compteur.timing.rpt
deleted file mode 100644
index a05c584..0000000
--- a/implementation/pnr/reports/compteur.timing.rpt
+++ /dev/null
@@ -1,34 +0,0 @@
-###############################################################
-# Generated by: Cadence Innovus 18.10-p002_1
-# OS: Linux x86_64(Host ID pcys41)
-# Generated on: Tue Oct 8 12:58:26 2019
-# Design: compteur
-# Command: report_timing > $::env(PNR_REP_DIR)/${DESIGN}.timing.rpt
-###############################################################
-Path 1: MET Late External Delay Assertion
-Endpoint: o_cnt[2] (v) checked with leading edge of 'clk'
-Beginpoint: cnt_reg[2]/Q (v) triggered by leading edge of 'clk'
-Path Groups: {clk}
-Analysis View: slow_av
-Other End Arrival Time 0.000
-- External Delay 0.200
-+ Phase Shift 1.250
-+ CPPR Adjustment 0.000
-- Uncertainty 0.100
-= Required Time 0.950
-- Arrival Time 0.796
-= Slack Time 0.154
- Clock Rise Edge 0.000
- + Clock Network Latency (Prop) -0.000
- = Beginpoint Arrival Time -0.000
- +---------------------------------------------------------------------------------+
- | Instance | Arc | Cell | Delay | Arrival | Required |
- | | | | | Time | Time |
- |--------------------------+-------------+-----------+-------+---------+----------|
- | cnt_reg[2] | CK ^ | | | -0.000 | 0.154 |
- | cnt_reg[2] | CK ^ -> Q v | SDFFRHQX1 | 0.239 | 0.239 | 0.393 |
- | FE_OFC20_FE_OFN3_o_cnt_2 | A v -> Y ^ | INVX2 | 0.095 | 0.334 | 0.488 |
- | FE_OFC21_FE_OFN3_o_cnt_2 | A ^ -> Y v | CLKINVX20 | 0.459 | 0.794 | 0.947 |
- | | o_cnt[2] v | | 0.003 | 0.796 | 0.950 |
- +---------------------------------------------------------------------------------+
-
diff --git a/implementation/pnr/reports/timing/compteur_postCTS.cap.gz b/implementation/pnr/reports/timing/compteur_postCTS.cap.gz
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diff --git a/implementation/pnr/reports/timing/compteur_prePlace_default.tarpt.gz b/implementation/pnr/reports/timing/compteur_prePlace_default.tarpt.gz
deleted file mode 100644
index b2e71bccda8e75f38704a5bc6a41cf7ebb408147..0000000000000000000000000000000000000000
GIT binary patch
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diff --git a/implementation/pnr/reports/timing/compteur_prePlace_reg2reg.tarpt.gz b/implementation/pnr/reports/timing/compteur_prePlace_reg2reg.tarpt.gz
deleted file mode 100644
index e252c8ab43854b43d91dba7d4ec0986f6c2d8e20..0000000000000000000000000000000000000000
GIT binary patch
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diff --git a/implementation/syn/netlist/compteur.elab.v b/implementation/syn/netlist/compteur.elab.v
deleted file mode 100644
index 65c5639..0000000
--- a/implementation/syn/netlist/compteur.elab.v
+++ /dev/null
@@ -1,154 +0,0 @@
-
-// Generated by Cadence Genus(TM) Synthesis Solution 18.10-p003_1
-// Generated on: Oct 8 2019 12:54:52 EDT (Oct 8 2019 16:54:52 UTC)
-
-// Verification Directory fv/compteur
-
-module add_unsigned(A, B, Z);
- input [3:0] A;
- input B;
- output [3:0] Z;
- wire [3:0] A;
- wire B;
- wire [3:0] Z;
- wire n_11, n_18, n_21, n_28, n_30, n_34, n_35, n_37;
- wire n_38;
- xor g1 (Z[0], A[0], B);
- nand g2 (n_11, A[0], B);
- nand g13 (n_21, n_18, A[1]);
- nand g20 (n_30, n_28, A[2]);
- xnor g25 (Z[1], n_18, n_34);
- xnor g27 (Z[2], n_28, n_35);
- xnor g30 (Z[3], n_37, n_38);
- not g35 (n_18, n_11);
- not g36 (n_34, A[1]);
- not g37 (n_35, A[2]);
- not g38 (n_38, A[3]);
- not g39 (n_28, n_21);
- not g40 (n_37, n_30);
-endmodule
-
-module bmux(ctl, in_0, in_1, z);
- input ctl;
- input [1:0] in_0, in_1;
- output [1:0] z;
- wire ctl;
- wire [1:0] in_0, in_1;
- wire [1:0] z;
- CDN_bmux2 g1(.sel0 (ctl), .data0 (in_0[1]), .data1 (in_1[1]), .z
- (z[1]));
- CDN_bmux2 g2(.sel0 (ctl), .data0 (in_0[0]), .data1 (in_1[0]), .z
- (z[0]));
-endmodule
-
-module bmux_7(ctl, in_0, in_1, z);
- input ctl;
- input [3:0] in_0, in_1;
- output [3:0] z;
- wire ctl;
- wire [3:0] in_0, in_1;
- wire [3:0] z;
- CDN_bmux2 g1(.sel0 (ctl), .data0 (in_0[3]), .data1 (in_1[3]), .z
- (z[3]));
- CDN_bmux2 g2(.sel0 (ctl), .data0 (in_0[2]), .data1 (in_1[2]), .z
- (z[2]));
- CDN_bmux2 g3(.sel0 (ctl), .data0 (in_0[1]), .data1 (in_1[1]), .z
- (z[1]));
- CDN_bmux2 g4(.sel0 (ctl), .data0 (in_0[0]), .data1 (in_1[0]), .z
- (z[0]));
-endmodule
-
-module compteur(i_clk, i_rstn, i_en, o_cnt);
- input i_clk, i_rstn, i_en;
- output [3:0] o_cnt;
- wire i_clk, i_rstn, i_en;
- wire [3:0] o_cnt;
- wire [3:0] plus_57_22;
- wire [1:0] rstn_sync;
- wire UNCONNECTED, UNCONNECTED0, UNCONNECTED1, UNCONNECTED2,
- UNCONNECTED3, UNCONNECTED4, n_20, n_21;
- wire n_23, n_24, n_25, n_26, n_27, n_43, n_44, n_46;
- add_unsigned add_57_22(.A (o_cnt), .B (1'b1), .Z (plus_57_22));
- bmux mux_rstn_sync_39_16(.ctl (n_20), .in_0 ({rstn_sync[0], 1'b1}),
- .in_1 (2'b00), .z ({UNCONNECTED0, UNCONNECTED}));
- bmux_7 mux_cnt_54_17(.ctl (n_23), .in_0 (plus_57_22), .in_1
- (4'b0000), .z ({n_27, n_26, n_25, n_24}));
- bmux_7 mux_cnt_50_14(.ctl (n_21), .in_0 ({n_27, n_26, n_25, n_24}),
- .in_1 (4'b0000), .z ({UNCONNECTED4, UNCONNECTED3, UNCONNECTED2,
- UNCONNECTED1}));
- CDN_flop \rstn_sync_reg[0] (.clk (i_clk), .d (1'b0), .sena (1'b0),
- .aclr (n_20), .apre (1'b0), .srl (1'b1), .srd (1'b1), .q
- (rstn_sync[0]));
- CDN_flop \rstn_sync_reg[1] (.clk (i_clk), .d (rstn_sync[0]), .sena
- (1'b1), .aclr (n_20), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q
- (rstn_sync[1]));
- CDN_flop \cnt_reg[0] (.clk (i_clk), .d (n_24), .sena (i_en), .aclr
- (n_21), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (o_cnt[0]));
- CDN_flop \cnt_reg[1] (.clk (i_clk), .d (n_25), .sena (i_en), .aclr
- (n_21), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (o_cnt[1]));
- CDN_flop \cnt_reg[2] (.clk (i_clk), .d (n_26), .sena (i_en), .aclr
- (n_21), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (o_cnt[2]));
- CDN_flop \cnt_reg[3] (.clk (i_clk), .d (n_27), .sena (i_en), .aclr
- (n_21), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (o_cnt[3]));
- nand g18 (n_46, o_cnt[0], n_43, n_44, o_cnt[3]);
- not g19 (n_23, n_46);
- not g20 (n_20, i_rstn);
- not g21 (n_21, rstn_sync[1]);
- not g22 (n_43, o_cnt[1]);
- not g23 (n_44, o_cnt[2]);
-endmodule
-
-`ifdef RC_CDN_GENERIC_GATE
-`else
-module CDN_flop(clk, d, sena, aclr, apre, srl, srd, q);
- input clk, d, sena, aclr, apre, srl, srd;
- output q;
- wire clk, d, sena, aclr, apre, srl, srd;
- wire q;
- reg qi;
- assign #1 q = qi;
- always
- @(posedge clk or posedge apre or posedge aclr)
- if (aclr)
- qi <= 0;
- else if (apre)
- qi <= 1;
- else if (srl)
- qi <= srd;
- else begin
- if (sena)
- qi <= d;
- end
- initial
- qi <= 1'b0;
-endmodule
-`endif
-`ifdef RC_CDN_GENERIC_GATE
-`else
-`ifdef ONE_HOT_MUX
-module CDN_bmux2(sel0, data0, data1, z);
- input sel0, data0, data1;
- output z;
- wire sel0, data0, data1;
- reg z;
- always
- @(sel0 or data0 or data1)
- case ({sel0})
- 1'b0: z = data0;
- 1'b1: z = data1;
- endcase
-endmodule
-`else
-module CDN_bmux2(sel0, data0, data1, z);
- input sel0, data0, data1;
- output z;
- wire sel0, data0, data1;
- wire z;
- wire inv_sel0, w_0, w_1;
- not i_0 (inv_sel0, sel0);
- and a_0 (w_0, inv_sel0, data0);
- and a_1 (w_1, sel0, data1);
- or org (z, w_0, w_1);
-endmodule
-`endif // ONE_HOT_MUX
-`endif
diff --git a/implementation/syn/netlist/compteur.syn.sdf b/implementation/syn/netlist/compteur.syn.sdf
deleted file mode 100644
index 9a80714..0000000
--- a/implementation/syn/netlist/compteur.syn.sdf
+++ /dev/null
@@ -1,323 +0,0 @@
-(DELAYFILE
- (SDFVERSION "OVI 2.1")
- (DESIGN "compteur")
- (DATE "Tue Oct 08 12:54:55 EDT 2019")
- (VENDOR "Cadence, Inc.")
- (PROGRAM "Genus(TM) Synthesis Solution")
- (VERSION "18.10-p003_1")
- (DIVIDER .)
- (VOLTAGE ::0.9)
- (PROCESS "::1.0")
- (TEMPERATURE ::125.0)
- (TIMESCALE 1ps)
- (CELL
- (CELLTYPE "DFFRHQX1")
- (INSTANCE rstn_sync_reg\[1\])
- (DELAY
- (ABSOLUTE
- (PORT RN (::0.0))
- (PORT CK (::0.0))
- (PORT D (::0.0))
- (IOPATH RN Q () (::71))
- (IOPATH CK Q (::227) (::198))
- )
- )
- (TIMINGCHECK
- (HOLD (posedge RN) (posedge CK) (::99))
- (RECOVERY (posedge RN) (posedge CK) (::0.0))
- (HOLD (negedge D) (posedge CK) (::0.0))
- (HOLD (posedge D) (posedge CK) (::0.0))
- (SETUP (negedge D) (posedge CK) (::76))
- (SETUP (posedge D) (posedge CK) (::135))
- )
- )
- (CELL
- (CELLTYPE "DFFRHQX1")
- (INSTANCE rstn_sync_reg\[0\])
- (DELAY
- (ABSOLUTE
- (PORT RN (::0.0))
- (PORT CK (::0.0))
- (PORT D (::0.0))
- (IOPATH RN Q () (::96))
- (IOPATH CK Q (::249) (::224))
- )
- )
- (TIMINGCHECK
- (HOLD (posedge RN) (posedge CK) (::99))
- (RECOVERY (posedge RN) (posedge CK) (::0.0))
- )
- )
- (CELL
- (CELLTYPE "DFFRHQX1")
- (INSTANCE cnt_reg\[3\])
- (DELAY
- (ABSOLUTE
- (PORT RN (::0.0))
- (PORT CK (::0.0))
- (PORT D (::0.0))
- (IOPATH RN Q () (::151))
- (IOPATH CK Q (::307) (::290))
- )
- )
- (TIMINGCHECK
- (HOLD (posedge RN) (posedge CK) (::91))
- (RECOVERY (posedge RN) (posedge CK) (::0.0))
- (HOLD (negedge D) (posedge CK) (::0.0))
- (HOLD (posedge D) (posedge CK) (::0.0))
- (SETUP (negedge D) (posedge CK) (::127))
- (SETUP (posedge D) (posedge CK) (::210))
- )
- )
- (CELL
- (CELLTYPE "SDFFRHQX1")
- (INSTANCE cnt_reg\[2\])
- (DELAY
- (ABSOLUTE
- (PORT RN (::0.0))
- (PORT CK (::0.0))
- (PORT D (::0.0))
- (PORT SI (::0.0))
- (PORT SE (::0.0))
- (IOPATH RN Q () (::148))
- (IOPATH CK Q (::307) (::287))
- )
- )
- (TIMINGCHECK
- (HOLD (posedge RN) (posedge CK) (::91))
- (RECOVERY (posedge RN) (posedge CK) (::0.0))
- (HOLD (negedge D) (posedge CK) (::0.0))
- (HOLD (posedge D) (posedge CK) (::0.0))
- (SETUP (negedge D) (posedge CK) (::166))
- (SETUP (posedge D) (posedge CK) (::242))
- (HOLD (negedge SI) (posedge CK) (::0.0))
- (HOLD (posedge SI) (posedge CK) (::0.0))
- (SETUP (negedge SI) (posedge CK) (::254))
- (SETUP (posedge SI) (posedge CK) (::266))
- (HOLD (negedge SE) (posedge CK) (::0.0))
- (HOLD (posedge SE) (posedge CK) (::0.0))
- (SETUP (negedge SE) (posedge CK) (::278))
- (SETUP (posedge SE) (posedge CK) (::246))
- )
- )
- (CELL
- (CELLTYPE "OAI31X1")
- (INSTANCE g337__8780)
- (DELAY
- (ABSOLUTE
- (PORT A0 (::0.0))
- (PORT A1 (::0.0))
- (PORT A2 (::0.0))
- (PORT B0 (::0.0))
- (IOPATH A0 Y (::250) (::223))
- (IOPATH B0 Y (::141) (::207))
- (IOPATH A1 Y (::187) (::153))
- (IOPATH A2 Y (::263) (::184))
- )
- )
- )
- (CELL
- (CELLTYPE "SDFFRHQX1")
- (INSTANCE cnt_reg\[1\])
- (DELAY
- (ABSOLUTE
- (PORT RN (::0.0))
- (PORT CK (::0.0))
- (PORT D (::0.0))
- (PORT SI (::0.0))
- (PORT SE (::0.0))
- (IOPATH RN Q () (::183))
- (IOPATH CK Q (::336) (::322))
- )
- )
- (TIMINGCHECK
- (HOLD (posedge RN) (posedge CK) (::91))
- (RECOVERY (posedge RN) (posedge CK) (::0.0))
- (HOLD (negedge D) (posedge CK) (::0.0))
- (HOLD (posedge D) (posedge CK) (::0.0))
- (SETUP (negedge D) (posedge CK) (::240))
- (SETUP (posedge D) (posedge CK) (::301))
- (HOLD (negedge SI) (posedge CK) (::0.0))
- (HOLD (posedge SI) (posedge CK) (::0.0))
- (SETUP (negedge SI) (posedge CK) (::178))
- (SETUP (posedge SI) (posedge CK) (::256))
- (HOLD (negedge SE) (posedge CK) (::0.0))
- (HOLD (posedge SE) (posedge CK) (::0.0))
- (SETUP (negedge SE) (posedge CK) (::230))
- (SETUP (posedge SE) (posedge CK) (::196))
- )
- )
- (CELL
- (CELLTYPE "AOI22X1")
- (INSTANCE g339__4296)
- (DELAY
- (ABSOLUTE
- (PORT A0 (::0.0))
- (PORT A1 (::0.0))
- (PORT B0 (::0.0))
- (PORT B1 (::0.0))
- (IOPATH A0 Y (::209) (::224))
- (IOPATH B0 Y (::223) (::217))
- (IOPATH A1 Y (::193) (::203))
- (IOPATH B1 Y (::132) (::136))
- )
- )
- )
- (CELL
- (CELLTYPE "DFFRHQX1")
- (INSTANCE cnt_reg\[0\])
- (DELAY
- (ABSOLUTE
- (PORT RN (::0.0))
- (PORT CK (::0.0))
- (PORT D (::0.0))
- (IOPATH RN Q () (::136))
- (IOPATH CK Q (::295) (::275))
- )
- )
- (TIMINGCHECK
- (HOLD (posedge RN) (posedge CK) (::91))
- (RECOVERY (posedge RN) (posedge CK) (::0.0))
- (HOLD (negedge D) (posedge CK) (::0.0))
- (HOLD (posedge D) (posedge CK) (::0.0))
- (SETUP (negedge D) (posedge CK) (::83))
- (SETUP (posedge D) (posedge CK) (::164))
- )
- )
- (CELL
- (CELLTYPE "INVX1")
- (INSTANCE g341)
- (DELAY
- (ABSOLUTE
- (PORT A (::0.0))
- (IOPATH A Y (::182) (::122))
- )
- )
- )
- (CELL
- (CELLTYPE "OAI21X1")
- (INSTANCE g342__3772)
- (DELAY
- (ABSOLUTE
- (PORT A0 (::0.0))
- (PORT A1 (::0.0))
- (PORT B0 (::0.0))
- (IOPATH A0 Y (::218) (::236))
- (IOPATH B0 Y (::70) (::138))
- (IOPATH A1 Y (::121) (::134))
- )
- )
- )
- (CELL
- (CELLTYPE "NAND2X1")
- (INSTANCE g343__1474)
- (DELAY
- (ABSOLUTE
- (PORT A (::0.0))
- (PORT B (::0.0))
- (IOPATH A Y (::202) (::280))
- (IOPATH B Y (::98) (::185))
- )
- )
- )
- (CELL
- (CELLTYPE "NOR2X1")
- (INSTANCE g344__4547)
- (DELAY
- (ABSOLUTE
- (PORT A (::0.0))
- (PORT B (::0.0))
- (IOPATH A Y (::204) (::171))
- (IOPATH B Y (::118) (::87))
- )
- )
- )
- (CELL
- (CELLTYPE "AOI2BB1X1")
- (INSTANCE g345__9682)
- (DELAY
- (ABSOLUTE
- (PORT A0N (::0.0))
- (PORT A1N (::0.0))
- (PORT B0 (::0.0))
- (IOPATH A1N Y (::172) (::178))
- (IOPATH B0 Y (::113) (::79))
- (IOPATH A0N Y (::131) (::136))
- )
- )
- )
- (CELL
- (CELLTYPE "AND2X1")
- (INSTANCE g346__2683)
- (DELAY
- (ABSOLUTE
- (PORT A (::0.0))
- (PORT B (::0.0))
- (IOPATH A Y (::169) (::119))
- (IOPATH B Y (::227) (::176))
- )
- )
- )
- (CELL
- (CELLTYPE "CLKAND2X3")
- (INSTANCE g347__1309)
- (DELAY
- (ABSOLUTE
- (PORT A (::0.0))
- (PORT B (::0.0))
- (IOPATH A Y (::117) (::111))
- (IOPATH B Y (::155) (::163))
- )
- )
- )
- (CELL
- (CELLTYPE "INVX3")
- (INSTANCE g348)
- (DELAY
- (ABSOLUTE
- (PORT A (::0.0))
- (IOPATH A Y (::109) (::109))
- )
- )
- )
- (CELL
- (CELLTYPE "CLKBUFX20")
- (INSTANCE drc_bufs351)
- (DELAY
- (ABSOLUTE
- (PORT A (::0.0))
- (IOPATH A Y (::479) (::558))
- )
- )
- )
- (CELL
- (CELLTYPE "CLKBUFX20")
- (INSTANCE drc_bufs354)
- (DELAY
- (ABSOLUTE
- (PORT A (::0.0))
- (IOPATH A Y (::452) (::529))
- )
- )
- )
- (CELL
- (CELLTYPE "CLKBUFX20")
- (INSTANCE drc_bufs357)
- (DELAY
- (ABSOLUTE
- (PORT A (::0.0))
- (IOPATH A Y (::452) (::527))
- )
- )
- )
- (CELL
- (CELLTYPE "CLKBUFX20")
- (INSTANCE drc_bufs360)
- (DELAY
- (ABSOLUTE
- (PORT A (::0.0))
- (IOPATH A Y (::441) (::516))
- )
- )
- )
-)
diff --git a/implementation/syn/netlist/compteur.syn.v b/implementation/syn/netlist/compteur.syn.v
deleted file mode 100644
index a3a1059..0000000
--- a/implementation/syn/netlist/compteur.syn.v
+++ /dev/null
@@ -1,44 +0,0 @@
-
-// Generated by Cadence Genus(TM) Synthesis Solution 18.10-p003_1
-// Generated on: Oct 8 2019 12:54:55 EDT (Oct 8 2019 16:54:55 UTC)
-
-// Verification Directory fv/compteur
-
-module compteur(i_clk, i_rstn, i_en, o_cnt);
- input i_clk, i_rstn, i_en;
- output [3:0] o_cnt;
- wire i_clk, i_rstn, i_en;
- wire [3:0] o_cnt;
- wire [1:0] rstn_sync;
- wire n_0, n_1, n_2, n_3, n_4, n_5, n_6, n_7;
- wire n_8, n_9, n_10, n_11, n_12, n_13;
- DFFRHQX1 \rstn_sync_reg[1] (.RN (i_rstn), .CK (i_clk), .D
- (rstn_sync[0]), .Q (rstn_sync[1]));
- DFFRHQX1 \rstn_sync_reg[0] (.RN (i_rstn), .CK (i_clk), .D (1'b1), .Q
- (rstn_sync[0]));
- DFFRHQX1 \cnt_reg[3] (.RN (rstn_sync[1]), .CK (i_clk), .D (n_9), .Q
- (n_13));
- SDFFRHQX1 \cnt_reg[2] (.RN (rstn_sync[1]), .CK (i_clk), .D (n_6), .SI
- (n_7), .SE (n_12), .Q (n_12));
- OAI31X1 g337__8780(.A0 (n_13), .A1 (n_0), .A2 (n_7), .B0 (n_8), .Y
- (n_9));
- SDFFRHQX1 \cnt_reg[1] (.RN (rstn_sync[1]), .CK (i_clk), .D (n_11),
- .SI (n_4), .SE (n_1), .Q (n_11));
- AOI22X1 g339__4296(.A0 (n_13), .A1 (n_5), .B0 (n_11), .B1 (n_2), .Y
- (n_8));
- DFFRHQX1 \cnt_reg[0] (.RN (rstn_sync[1]), .CK (i_clk), .D (n_3), .Q
- (n_10));
- INVX1 g341(.A (n_7), .Y (n_6));
- OAI21X1 g342__3772(.A0 (n_11), .A1 (n_0), .B0 (n_1), .Y (n_5));
- NAND2X1 g343__1474(.A (n_11), .B (n_1), .Y (n_7));
- NOR2X1 g344__4547(.A (n_11), .B (n_2), .Y (n_4));
- AOI2BB1X1 g345__9682(.A0N (i_en), .A1N (n_10), .B0 (n_1), .Y (n_3));
- AND2X1 g346__2683(.A (n_0), .B (n_13), .Y (n_2));
- CLKAND2X3 g347__1309(.A (i_en), .B (n_10), .Y (n_1));
- INVX3 g348(.A (n_12), .Y (n_0));
- CLKBUFX20 drc_bufs351(.A (n_11), .Y (o_cnt[1]));
- CLKBUFX20 drc_bufs354(.A (n_13), .Y (o_cnt[3]));
- CLKBUFX20 drc_bufs357(.A (n_12), .Y (o_cnt[2]));
- CLKBUFX20 drc_bufs360(.A (n_10), .Y (o_cnt[0]));
-endmodule
-
diff --git a/implementation/syn/reports/compteur.check.rpt b/implementation/syn/reports/compteur.check.rpt
deleted file mode 100644
index 527cade..0000000
--- a/implementation/syn/reports/compteur.check.rpt
+++ /dev/null
@@ -1,615 +0,0 @@
-
- Check Design Report
- --------------------
-
- Long Module Names
-----------------------
-No subdesign's name is greater than 1.5k in length.
-
- Unresolved References & Empty Modules
- -------------------------------------
-No unresolved references in design 'compteur'
-
-No empty modules in design 'compteur'
-
- Unloaded Pin(s), Port(s)
- -------------------------
-No unloaded sequential element in 'compteur'
-
-No unloaded port in 'compteur'
-
- Unloaded Combinational Pin(s)
- -------------------------------
-No unloaded combinational element in 'compteur'
-
- Assigns
- -------
-Total number of assign statements in design 'compteur' : 0
-
- Undriven Port(s)/Pin(s)
- ------------------------
-No undriven combinational pin in 'compteur'
-
-No undriven sequential pin in 'compteur'
-
-No undriven hierarchical pin in 'compteur'
-
-No undriven port in 'compteur'
-
- Multidriven Port(s)/Pin(s)
---------------------------
-
-No multidriven combinational pin in 'compteur'
-
-No multidriven sequential pin in 'compteur'
-
-No multidriven hierarchical pin in 'compteur'
-
-No multidriven ports in 'compteur'
-
-No multidriven unloaded nets in 'compteur'
-
- Constant Pin(s)
- ----------------
-No constant combinational pin(s) in design 'compteur'
-
-No constant sequential pin(s) in design 'compteur'
-
-design 'compteur' has the following constant input hierarchical pin(s)
-hpin:compteur/add_57_22/B (fanout : 2)
-hpin:compteur/mux_rstn_sync_39_16/in_1[0] (fanout : 1)
-hpin:compteur/mux_rstn_sync_39_16/in_1[1] (fanout : 1)
-hpin:compteur/mux_cnt_54_17/in_1[0] (fanout : 1)
-hpin:compteur/mux_cnt_54_17/in_1[1] (fanout : 1)
-hpin:compteur/mux_cnt_54_17/in_1[2] (fanout : 1)
-hpin:compteur/mux_cnt_54_17/in_1[3] (fanout : 1)
-hpin:compteur/mux_cnt_50_14/in_1[0] (fanout : 1)
-hpin:compteur/mux_cnt_50_14/in_1[1] (fanout : 1)
-hpin:compteur/mux_cnt_50_14/in_1[2] (fanout : 1)
-hpin:compteur/mux_cnt_50_14/in_1[3] (fanout : 1)
-hpin:compteur/mux_rstn_sync_39_16/in_0[0] (fanout : 1)
-Total number of constant hierarchical pins in design 'compteur' : 12
-
-No constant connected ports in design 'compteur'
-
- Preserved instances(s)
- ----------------
-No preserved combinational instance(s) in design 'compteur'
-No preserved sequential instance(s) in design 'compteur'
-No preserved hierarchical instance(s) in design 'compteur'
-
- Physical only instances(s)
- ----------------
-No physical only instance(s) in design 'compteur'
-
- Logical only instance(s) and linked libcells
- -----------------------------------------
-No logical only instance(s) in design 'compteur'
-
-Libcells with no corresponding LEF
-----------------------------------
-lib_cell:default_emulate_libset_max/slow_vdd1v0/ACHCONX2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/ADDFHX1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/ADDFHX2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/ADDFHX4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/ADDFHXL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/ADDFX1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/ADDFX2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/ADDFX4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/ADDFXL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/ADDHX1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/ADDHX2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/ADDHX4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/ADDHXL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/AND2X1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/AND2X2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/AND2X4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/AND2X6
-lib_cell:default_emulate_libset_max/slow_vdd1v0/AND2X8
-lib_cell:default_emulate_libset_max/slow_vdd1v0/AND2XL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/AND3X1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/AND3X2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/AND3X4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/AND3X6
-lib_cell:default_emulate_libset_max/slow_vdd1v0/AND3X8
-lib_cell:default_emulate_libset_max/slow_vdd1v0/AND3XL
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-lib_cell:default_emulate_libset_max/slow_vdd1v0/NOR4BX1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/NOR4BX2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/NOR4BX4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/NOR4BXL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/NOR4X1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/NOR4X2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/NOR4X4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/NOR4X6
-lib_cell:default_emulate_libset_max/slow_vdd1v0/NOR4X8
-lib_cell:default_emulate_libset_max/slow_vdd1v0/NOR4XL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OA21X1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OA21X2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OA21X4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OA21XL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OA22X1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OA22X2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OA22X4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OA22XL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI211X1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI211X2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI211X4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI211XL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI21X1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI21X2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI21X4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI21XL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI221X1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI221X2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI221X4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI221XL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI222X1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI222X2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI222X4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI222XL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI22X1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI22X2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI22X4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI22XL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI2BB1X1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI2BB1X2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI2BB1X4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI2BB1XL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI2BB2X1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI2BB2X2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI2BB2X4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI2BB2XL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI31X1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI31X2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI31X4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI31XL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI32X1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI32X2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI32X4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI32XL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI33X1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI33X2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI33X4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OAI33XL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OR2X1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OR2X2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OR2X4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OR2X6
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OR2X8
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OR2XL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OR3X1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OR3X2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OR3X4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OR3X6
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OR3X8
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OR3XL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OR4X1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OR4X2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OR4X4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OR4X6
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OR4X8
-lib_cell:default_emulate_libset_max/slow_vdd1v0/OR4XL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFHQX1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFHQX2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFHQX4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFHQX8
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFNSRX1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFNSRX2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFNSRX4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFNSRXL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFQX1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFQX2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFQX4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFQXL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFRHQX1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFRHQX2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFRHQX4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFRHQX8
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFRX1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFRX2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFRX4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFRXL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSHQX1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSHQX2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSHQX4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSHQX8
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSRHQX1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSRHQX2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSRHQX4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSRHQX8
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSRX1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSRX2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSRX4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSRXL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSX1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSX2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSX4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSXL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFTRX1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFTRX2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFTRX4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFTRXL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFX1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFX2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFX4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFXL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SEDFFHQX1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SEDFFHQX2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SEDFFHQX4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SEDFFHQX8
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SEDFFTRX1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SEDFFTRX2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SEDFFTRX4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SEDFFTRXL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SEDFFX1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SEDFFX2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SEDFFX4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SEDFFXL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SMDFFHQX1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SMDFFHQX2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SMDFFHQX4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/SMDFFHQX8
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TBUFX1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TBUFX12
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TBUFX16
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TBUFX2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TBUFX20
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TBUFX3
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TBUFX4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TBUFX6
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TBUFX8
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TBUFXL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TIEHI
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TIELO
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNCAX12
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNCAX16
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNCAX2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNCAX20
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNCAX3
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNCAX4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNCAX6
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNCAX8
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNSRX1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNSRX2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNSRX4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNSRXL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNTSCAX12
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNTSCAX16
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNTSCAX2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNTSCAX20
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNTSCAX3
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNTSCAX4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNTSCAX6
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNTSCAX8
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNX1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNX2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNX4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNXL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATSRX1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATSRX2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATSRX4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATSRXL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATX1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATX2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATX4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATXL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/XNOR2X1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/XNOR2X2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/XNOR2X4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/XNOR2XL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/XNOR3X1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/XNOR3XL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/XOR2X1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/XOR2X2
-lib_cell:default_emulate_libset_max/slow_vdd1v0/XOR2X4
-lib_cell:default_emulate_libset_max/slow_vdd1v0/XOR2XL
-lib_cell:default_emulate_libset_max/slow_vdd1v0/XOR3X1
-lib_cell:default_emulate_libset_max/slow_vdd1v0/XOR3XL
-
-Total number of cell(s) with only library (.lib) info : 489
-
-LEF cells with no corresponding libcell
----------------------------------------
-
-No physical (LEF) cells found.
-
- Summary
- -------
-
- Name Total
--------------------------------------------
-Unresolved References 0
-Empty Modules 0
-Unloaded Port(s) 0
-Unloaded Sequential Pin(s) 0
-Unloaded Combinational Pin(s) 0
-Assigns 0
-Undriven Port(s) 0
-Undriven Leaf Pin(s) 0
-Undriven hierarchical pin(s) 0
-Multidriven Port(s) 0
-Multidriven Leaf Pin(s) 0
-Multidriven hierarchical Pin(s) 0
-Multidriven unloaded net(s) 0
-Constant Port(s) 0
-Constant Leaf Pin(s) 0
-Constant hierarchical Pin(s) 12
-Preserved leaf instance(s) 0
-Preserved hierarchical instance(s) 0
-Libcells with no LEF cell 489
-Physical (LEF) cells with no libcell 0
-Subdesigns with long module name 0
-Physical only instance(s) 0
-Logical only instance(s) 0
diff --git a/implementation/syn/reports/compteur.clk.rpt b/implementation/syn/reports/compteur.clk.rpt
deleted file mode 100644
index ecad885..0000000
--- a/implementation/syn/reports/compteur.clk.rpt
+++ /dev/null
@@ -1,45 +0,0 @@
-============================================================
- Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
- Generated on: Oct 08 2019 12:54:52 pm
- Module: compteur
- Technology library: slow_vdd1v0 1.0
- Operating conditions: PVT_0P9V_125C
- Interconnect mode: global
- Area mode: timing library
-============================================================
-
-
- Clock Description
- -----------------
-
- Clock Clock Source No of
- Name Period Rise Fall Domain Pin/Port Registers
--------------------------------------------------------------
- clk 1250.0 0.0 625.0 domain_1 i_clk 6
-
- Clock Network Latency / Setup Uncertainty
- -----------------------------------------
-
- Network Network Source Source Setup Setup
-Clock Latency Latency Latency Latency Uncertainty Uncertainty
- Name Rise Fall Rise Fall Rise Fall
-----------------------------------------------------------------------
-clk 0.0 0.0 0.0 0.0 100.0 100.0
-
- Clock Relationship (with uncertainty & latency)
- -----------------------------------------------
-
- From To R->R R->F F->R F->F
------------------------------------------------
- clk clk 1150.0 525.0 525.0 1150.0
-============================================================
- Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
- Generated on: Oct 08 2019 12:54:52 pm
- Module: compteur
- Technology library: slow_vdd1v0 1.0
- Operating conditions: PVT_0P9V_125C
- Interconnect mode: global
- Area mode: timing library
-============================================================
-
-No clocks to report
diff --git a/implementation/syn/reports/compteur.gen.area.rpt b/implementation/syn/reports/compteur.gen.area.rpt
deleted file mode 100644
index ae2cfb4..0000000
--- a/implementation/syn/reports/compteur.gen.area.rpt
+++ /dev/null
@@ -1,12 +0,0 @@
-============================================================
- Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
- Generated on: Oct 08 2019 12:54:53 pm
- Module: compteur
- Operating conditions: PVT_0P9V_125C
- Interconnect mode: global
- Area mode: timing library
-============================================================
-
-Instance Module Cell Count Cell Area Net Area Total Area
---------------------------------------------------------------
-compteur 34 128.126 2.965 131.091
diff --git a/implementation/syn/reports/compteur.gen.gates.rpt b/implementation/syn/reports/compteur.gen.gates.rpt
deleted file mode 100644
index ad850d6..0000000
--- a/implementation/syn/reports/compteur.gen.gates.rpt
+++ /dev/null
@@ -1,19 +0,0 @@
-============================================================
- Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
- Generated on: Oct 08 2019 12:54:53 pm
- Module: compteur
- Operating conditions: PVT_0P9V_125C
- Interconnect mode: global
- Area mode: timing library
-============================================================
-
-
- Type Instances Area Area %
---------------------------------------
-sequential 6 0.000 0.0
-inverter 2 0.000 0.0
-logic 26 0.000 0.0
-physical_cells 0 0.000 0.0
---------------------------------------
-total 34 0.000 0.0
-
diff --git a/implementation/syn/reports/compteur.gen.power.rpt b/implementation/syn/reports/compteur.gen.power.rpt
deleted file mode 100644
index 5ac205c..0000000
--- a/implementation/syn/reports/compteur.gen.power.rpt
+++ /dev/null
@@ -1,14 +0,0 @@
-============================================================
- Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
- Generated on: Oct 08 2019 12:54:53 pm
- Module: compteur
- Operating conditions: PVT_0P9V_125C
- Interconnect mode: global
- Area mode: timing library
-============================================================
-
- Leakage Dynamic Total
-Instance Cells Power(nW) Power(nW) Power(nW)
-------------------------------------------------
-compteur 34 0.799 127636.633 127637.432
-
diff --git a/implementation/syn/reports/compteur.gen.timing.rpt b/implementation/syn/reports/compteur.gen.timing.rpt
deleted file mode 100644
index cd22116..0000000
--- a/implementation/syn/reports/compteur.gen.timing.rpt
+++ /dev/null
@@ -1,47 +0,0 @@
-============================================================
- Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
- Generated on: Oct 08 2019 12:54:53 pm
- Module: compteur
- Operating conditions: PVT_0P9V_125C
- Interconnect mode: global
- Area mode: timing library
-============================================================
-
-
-Path 1: MET (146 ps) Setup Check with Pin cnt_reg[3]/clk->d
- Group: clk
- Startpoint: (R) cnt_reg[1]/clk
- Clock: (R) clk
- Endpoint: (R) cnt_reg[3]/d
- Clock: (R) clk
-
- Capture Launch
- Clock Edge:+ 1250 0
- Src Latency:+ 0 0
- Net Latency:+ 0 (I) 0 (I)
- Arrival:= 1250 0
-
- Setup:- 119
- Uncertainty:- 100
- Required Time:= 1031
- Launch Clock:- 0
- Data Path:- 885
- Slack:= 146
-
-#--------------------------------------------------------------------------------------------------
-# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance
-# (fF) (ps) (ps) (ps) Location
-#--------------------------------------------------------------------------------------------------
- cnt_reg[1]/clk - - R (arrival) 6 - 0 - 0 (-,-)
- cnt_reg[1]/q (u) clk->q F unmapped_d_flop 6 506.6 0 454 454 (-,-)
- g173/z (u) in_1->z R unmapped_nand2 2 2.0 0 79 533 (-,-)
- g162/z (u) in_0->z R unmapped_complex2 2 2.0 0 79 611 (-,-)
- g160/z (u) in_0->z F unmapped_nand2 1 1.0 0 68 680 (-,-)
- g154/z (u) in_1->z R unmapped_nand2 1 1.0 0 68 748 (-,-)
- g152/z (u) in_0->z F unmapped_nand2 1 1.0 0 68 816 (-,-)
- g151/z (u) in_0->z R unmapped_nand2 1 1.0 0 68 885 (-,-)
- cnt_reg[3]/d <<< - R unmapped_d_flop 1 - - 0 885 (-,-)
-#--------------------------------------------------------------------------------------------------
-
-(u) : Net has unmapped pin(s).
-
diff --git a/implementation/syn/reports/compteur.hier_elab.rpt b/implementation/syn/reports/compteur.hier_elab.rpt
deleted file mode 100644
index 775485a..0000000
--- a/implementation/syn/reports/compteur.hier_elab.rpt
+++ /dev/null
@@ -1,17 +0,0 @@
-============================================================
- Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
- Generated on: Oct 08 2019 12:54:52 pm
- Module: compteur
- Technology library: slow_vdd1v0 1.0
- Operating conditions: PVT_0P9V_125C
- Interconnect mode: global
- Area mode: timing library
-============================================================
-
- Instance Cell Count TNS Cells(same hier) TNS(same hier)
--------------------------------------------------------------------------
-compteur 35 0 0 0
- add_57_22 13 0 0
- mux_cnt_50_14 4 0 0
- mux_cnt_54_17 4 0 0
- mux_rstn_sync_39_16 2 0 0
diff --git a/implementation/syn/reports/compteur.map.area.rpt b/implementation/syn/reports/compteur.map.area.rpt
deleted file mode 100644
index c720e63..0000000
--- a/implementation/syn/reports/compteur.map.area.rpt
+++ /dev/null
@@ -1,12 +0,0 @@
-============================================================
- Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
- Generated on: Oct 08 2019 12:54:54 pm
- Module: compteur
- Operating conditions: PVT_0P9V_125C
- Interconnect mode: global
- Area mode: timing library
-============================================================
-
-Instance Module Cell Count Cell Area Net Area Total Area
---------------------------------------------------------------
-compteur 20 90.972 22.408 113.380
diff --git a/implementation/syn/reports/compteur.map.gates.rpt b/implementation/syn/reports/compteur.map.gates.rpt
deleted file mode 100644
index 446c874..0000000
--- a/implementation/syn/reports/compteur.map.gates.rpt
+++ /dev/null
@@ -1,40 +0,0 @@
-============================================================
- Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
- Generated on: Oct 08 2019 12:54:54 pm
- Module: compteur
- Operating conditions: PVT_0P9V_125C
- Interconnect mode: global
- Area mode: timing library
-============================================================
-
-
- Gate Instances Area Library
---------------------------------------------
-AND2X1 1 1.368 slow_vdd1v0
-AOI22X1 1 2.052 slow_vdd1v0
-AOI2BB1X1 1 2.052 slow_vdd1v0
-CLKAND2X3 1 3.078 slow_vdd1v0
-CLKBUFX20 4 32.832 slow_vdd1v0
-DFFRHQX1 4 24.624 slow_vdd1v0
-INVX1 1 0.684 slow_vdd1v0
-INVX3 1 1.368 slow_vdd1v0
-NAND2X2 1 1.710 slow_vdd1v0
-NOR2X1 1 1.026 slow_vdd1v0
-OAI21X1 1 1.710 slow_vdd1v0
-OAI31X1 1 2.052 slow_vdd1v0
-SDFFRHQX1 2 16.416 slow_vdd1v0
---------------------------------------------
-total 20 90.972
-
-
-
- Type Instances Area Area %
----------------------------------------
-sequential 6 41.040 45.1
-inverter 2 2.052 2.3
-buffer 4 32.832 36.1
-logic 8 15.048 16.5
-physical_cells 0 0.000 0.0
----------------------------------------
-total 20 90.972 100.0
-
diff --git a/implementation/syn/reports/compteur.map.power.rpt b/implementation/syn/reports/compteur.map.power.rpt
deleted file mode 100644
index 5bb9d0e..0000000
--- a/implementation/syn/reports/compteur.map.power.rpt
+++ /dev/null
@@ -1,14 +0,0 @@
-============================================================
- Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
- Generated on: Oct 08 2019 12:54:54 pm
- Module: compteur
- Operating conditions: PVT_0P9V_125C
- Interconnect mode: global
- Area mode: timing library
-============================================================
-
- Leakage Dynamic Total
-Instance Cells Power(nW) Power(nW) Power(nW)
-------------------------------------------------
-compteur 20 3.850 321043.714 321047.564
-
diff --git a/implementation/syn/reports/compteur.map.timing.rpt b/implementation/syn/reports/compteur.map.timing.rpt
deleted file mode 100644
index 6f3f09b..0000000
--- a/implementation/syn/reports/compteur.map.timing.rpt
+++ /dev/null
@@ -1,43 +0,0 @@
-============================================================
- Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
- Generated on: Oct 08 2019 12:54:54 pm
- Module: compteur
- Operating conditions: PVT_0P9V_125C
- Interconnect mode: global
- Area mode: timing library
-============================================================
-
-
-Path 1: MET (32 ps) Setup Check with Pin cnt_reg[3]/CK->D
- Group: clk
- Startpoint: (R) cnt_reg[0]/CK
- Clock: (R) clk
- Endpoint: (F) cnt_reg[3]/D
- Clock: (R) clk
-
- Capture Launch
- Clock Edge:+ 1250 0
- Src Latency:+ 0 0
- Net Latency:+ 0 (I) 0 (I)
- Arrival:= 1250 0
-
- Setup:- 127
- Uncertainty:- 100
- Required Time:= 1023
- Launch Clock:- 0
- Data Path:- 991
- Slack:= 32
-
-#---------------------------------------------------------------------------------------
-# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance
-# (fF) (ps) (ps) (ps) Location
-#---------------------------------------------------------------------------------------
- cnt_reg[0]/CK - - R (arrival) 6 - 0 - 0 (-,-)
- cnt_reg[0]/Q - CK->Q R DFFRHQX1 3 5.9 135 295 295 (-,-)
- g347__1309/Y - B->Y R CLKAND2X3 4 6.2 59 156 451 (-,-)
- g342__3772/Y - B0->Y F OAI21X1 1 2.0 166 139 590 (-,-)
- g339__4296/Y - A1->Y R AOI22X1 1 2.0 160 193 783 (-,-)
- g337__8780/Y - B0->Y F OAI31X1 1 1.9 172 208 991 (-,-)
- cnt_reg[3]/D <<< - F DFFRHQX1 1 - - 0 991 (-,-)
-#---------------------------------------------------------------------------------------
-
diff --git a/implementation/syn/reports/compteur.syn.area.rpt b/implementation/syn/reports/compteur.syn.area.rpt
deleted file mode 100644
index 8d586d6..0000000
--- a/implementation/syn/reports/compteur.syn.area.rpt
+++ /dev/null
@@ -1,12 +0,0 @@
-============================================================
- Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
- Generated on: Oct 08 2019 12:54:55 pm
- Module: compteur
- Operating conditions: PVT_0P9V_125C
- Interconnect mode: global
- Area mode: timing library
-============================================================
-
-Instance Module Cell Count Cell Area Net Area Total Area
---------------------------------------------------------------
-compteur 20 90.288 22.408 112.696
diff --git a/implementation/syn/reports/compteur.syn.gates.rpt b/implementation/syn/reports/compteur.syn.gates.rpt
deleted file mode 100644
index 71aa59a..0000000
--- a/implementation/syn/reports/compteur.syn.gates.rpt
+++ /dev/null
@@ -1,40 +0,0 @@
-============================================================
- Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
- Generated on: Oct 08 2019 12:54:55 pm
- Module: compteur
- Operating conditions: PVT_0P9V_125C
- Interconnect mode: global
- Area mode: timing library
-============================================================
-
-
- Gate Instances Area Library
---------------------------------------------
-AND2X1 1 1.368 slow_vdd1v0
-AOI22X1 1 2.052 slow_vdd1v0
-AOI2BB1X1 1 2.052 slow_vdd1v0
-CLKAND2X3 1 3.078 slow_vdd1v0
-CLKBUFX20 4 32.832 slow_vdd1v0
-DFFRHQX1 4 24.624 slow_vdd1v0
-INVX1 1 0.684 slow_vdd1v0
-INVX3 1 1.368 slow_vdd1v0
-NAND2X1 1 1.026 slow_vdd1v0
-NOR2X1 1 1.026 slow_vdd1v0
-OAI21X1 1 1.710 slow_vdd1v0
-OAI31X1 1 2.052 slow_vdd1v0
-SDFFRHQX1 2 16.416 slow_vdd1v0
---------------------------------------------
-total 20 90.288
-
-
-
- Type Instances Area Area %
----------------------------------------
-sequential 6 41.040 45.5
-inverter 2 2.052 2.3
-buffer 4 32.832 36.4
-logic 8 14.364 15.9
-physical_cells 0 0.000 0.0
----------------------------------------
-total 20 90.288 100.0
-
diff --git a/implementation/syn/reports/compteur.syn.power.rpt b/implementation/syn/reports/compteur.syn.power.rpt
deleted file mode 100644
index 44407f3..0000000
--- a/implementation/syn/reports/compteur.syn.power.rpt
+++ /dev/null
@@ -1,14 +0,0 @@
-============================================================
- Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
- Generated on: Oct 08 2019 12:54:55 pm
- Module: compteur
- Operating conditions: PVT_0P9V_125C
- Interconnect mode: global
- Area mode: timing library
-============================================================
-
- Leakage Dynamic Total
-Instance Cells Power(nW) Power(nW) Power(nW)
-------------------------------------------------
-compteur 20 3.823 320889.077 320892.900
-
diff --git a/implementation/syn/reports/compteur.syn.timing.rpt b/implementation/syn/reports/compteur.syn.timing.rpt
deleted file mode 100644
index fac5ca0..0000000
--- a/implementation/syn/reports/compteur.syn.timing.rpt
+++ /dev/null
@@ -1,43 +0,0 @@
-============================================================
- Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
- Generated on: Oct 08 2019 12:54:55 pm
- Module: compteur
- Operating conditions: PVT_0P9V_125C
- Interconnect mode: global
- Area mode: timing library
-============================================================
-
-
-Path 1: MET (36 ps) Setup Check with Pin cnt_reg[3]/CK->D
- Group: clk
- Startpoint: (R) cnt_reg[0]/CK
- Clock: (R) clk
- Endpoint: (F) cnt_reg[3]/D
- Clock: (R) clk
-
- Capture Launch
- Clock Edge:+ 1250 0
- Src Latency:+ 0 0
- Net Latency:+ 0 (I) 0 (I)
- Arrival:= 1250 0
-
- Setup:- 127
- Uncertainty:- 100
- Required Time:= 1023
- Launch Clock:- 0
- Data Path:- 987
- Slack:= 36
-
-#---------------------------------------------------------------------------------------
-# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance
-# (fF) (ps) (ps) (ps) Location
-#---------------------------------------------------------------------------------------
- cnt_reg[0]/CK - - R (arrival) 6 - 0 - 0 (-,-)
- cnt_reg[0]/Q - CK->Q R DFFRHQX1 3 5.9 135 295 295 (-,-)
- g347__1309/Y - B->Y R CLKAND2X3 4 5.8 56 155 449 (-,-)
- g342__3772/Y - B0->Y F OAI21X1 1 2.0 165 138 587 (-,-)
- g339__4296/Y - A1->Y R AOI22X1 1 2.0 159 193 780 (-,-)
- g337__8780/Y - B0->Y F OAI31X1 1 1.9 172 207 987 (-,-)
- cnt_reg[3]/D <<< - F DFFRHQX1 1 - - 0 987 (-,-)
-#---------------------------------------------------------------------------------------
-
diff --git a/implementation/syn/reports/compteur.timing_lint.rpt b/implementation/syn/reports/compteur.timing_lint.rpt
deleted file mode 100644
index d62caf3..0000000
--- a/implementation/syn/reports/compteur.timing_lint.rpt
+++ /dev/null
@@ -1,48 +0,0 @@
-============================================================
- Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
- Generated on: Oct 08 2019 12:54:52 pm
- Module: compteur
- Technology library: slow_vdd1v0 1.0
- Operating conditions: PVT_0P9V_125C
- Interconnect mode: global
- Area mode: timing library
-============================================================
-
--------------------------------------------------------------------------------
-Timing exceptions with no effect
-
-The following timing exceptions are not currently affecting timing in the
-design. Either no paths in the design satisfy the exception's path
-specification, or all paths that satisfy the path specification also satisfy an
-exception with a higher priority. You can improve runtime and memory usage by
-removing these exceptions if they are not truly needed. To see if there is a
-path in the design that satisfies the path specification for an exception, or
-to see what other exception is overriding an exception because of priority, use
-the command:
- report timing -paths [eval [::legacy::get_attribute paths <exception>]]
-
-exception:compteur/timing.sdc_line_28
--------------------------------------------------------------------------------
-
-
-Lint summary
- Unconnected/logic driven clocks 0
- Sequential data pins driven by a clock signal 0
- Sequential clock pins without clock waveform 0
- Sequential clock pins with multiple clock waveforms 0
- Generated clocks without clock waveform 0
- Generated clocks with incompatible options 0
- Generated clocks with multi-master clock 0
- Paths constrained with different clocks 0
- Loop-breaking cells for combinational feedback 0
- Nets with multiple drivers 0
- Timing exceptions with no effect 1
- Suspicious multi_cycle exceptions 0
- Pins/ports with conflicting case constants 0
- Inputs without clocked external delays 0
- Outputs without clocked external delays 0
- Inputs without external driver/transition 0
- Outputs without external load 0
- Exceptions with invalid timing start-/endpoints 0
-
- Total: 1
diff --git a/scripts/pnr.tcl b/scripts/pnr.tcl
deleted file mode 100644
index 105a1b0..0000000
--- a/scripts/pnr.tcl
+++ /dev/null
@@ -1,220 +0,0 @@
-#-----------------------------------------------------------------------------
-# Project Tutoriels - Conception de circuits intégrés numériques
-#-----------------------------------------------------------------------------
-# File pnr.tcl
-# Author Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
-# Lab GRM - Polytechnique Montreal
-# Date <2019-09-10 Tue>
-#-----------------------------------------------------------------------------
-# Brief Placement & Routage du mini-mips avec Innovus
-# Usage cd implementation
-# innovus -files ../scripts/syn.tcl
-#-----------------------------------------------------------------------------
-package require Tcl 8.5
-
-if { ![info exist ::env(PROJECT_HOME)] } {
- error "ERREUR: Configurer l'environnement (source setup.csh) avant d'utiliser ce script"
-}
-
-#-----------------------------------------------------------------------------
-# CONFIG
-#-----------------------------------------------------------------------------
-set DO_INIT 1
-set DO_FP 1
-set DO_POWER 1
-set DO_IO 1
-set DO_PLACE 1
-set DO_CTS 1
-set DO_ROUTE 1
-set DO_SAVE 1
-
-set DESIGN compteur
-
-# Répertoires de destination
-file mkdir $::env(PNR_REP_DIR) $::env(PNR_NET_DIR)
-set OPT_DIR $::env(PNR_DIR)/opt
-set TIM_DIR $::env(PNR_REP_DIR)/timing
-set OA_DIR compteur_oa
-
-#-----------------------------------------------------------------------------
-# INIT
-#-----------------------------------------------------------------------------
-if { $DO_INIT } {
-
- set init_oa_ref_lib [list gsclib045_tech gsclib045 giolib045]
- set init_verilog $::env(SYN_NET_DIR)/${DESIGN}.syn.v
- set init_design_settop 1
- set init_top_cell $DESIGN
- set init_gnd_net VSS
- set init_pwr_net VDD
- set init_mmmc_file $::env(CONST_DIR)/mmmc.tcl
-
- init_design
-}
-
-#-----------------------------------------------------------------------------
-# FLOORPLAN
-#-----------------------------------------------------------------------------
-if { $DO_FP } {
-
- floorPlan -site CoreSite -r 0.9 0.6 1 1 1 1
-}
-
-#-----------------------------------------------------------------------------
-# ALIMENTATIONS
-#-----------------------------------------------------------------------------
-if { $DO_POWER } {
-
- globalNetConnect VDD -type pgpin -pin VDD -inst * -override
- globalNetConnect VSS -type pgpin -pin VSS -inst * -override
- globalNetConnect VDD -type tiehi -inst * -override
- globalNetConnect VSS -type tielo -inst * -override
-
- addStripe -nets VDD \
- -layer Metal1 \
- -direction vertical \
- -width 0.6 \
- -number_of_sets 1 \
- -start_from left \
- -start_offset -0.8
-
- addStripe -nets VSS \
- -layer Metal1 \
- -direction vertical \
- -width 0.6 \
- -number_of_sets 1 \
- -start_from right \
- -start_offset -0.8
-
- sroute -nets { VDD VSS } \
- -connect { corePin floatingStripe } \
- -layerChangeRange { Metal1(1) Metal1(1) }
-}
-
-#-----------------------------------------------------------------------------
-# I/O
-#-----------------------------------------------------------------------------
-if { $DO_IO } {
-
- set top_nets [list [get_nets -quiet "i_clk"] \
- [get_nets -quiet "i_rstn"] \
- [get_nets -quiet "i_en"]]
-
- set bottom_nets [list [get_nets -quiet "o_cnt[*]"]]
-
- set top_n [list ]
- foreach nets $top_nets {foreach_in_collection n $nets {lappend top_n [get_object_name $n]}}
-
- set bottom_n [list ]
- foreach nets $bottom_nets {foreach_in_collection n $nets {lappend bottom_n [get_object_name $n]}}
-
- setPinAssignMode -pinEditInBatch true
-
- editPin -pin "${top_n}" -side Top -layer 2 \
- -pinWidth 0.06 -pinDepth 0.335 \
- -spreadDirection clockwise -spreadType range \
- -start 2 9.12 -end 10 9.12
-
- editPin -pin "${bottom_n}" -side Bottom -layer 2 \
- -pinWidth 0.08 -pinDepth 0.25 \
- -spreadDirection counterclockwise -spreadType range \
- -start 1 0 -end 11 0
-}
-
-#-----------------------------------------------------------------------------
-# PLACEMENT
-#-----------------------------------------------------------------------------
-if { $DO_PLACE } {
-
- # Timing
- timeDesign -prePlace -outDir ${TIM_DIR}
-
- # Placement
- setPlaceMode -place_global_reorder_scan false
- deleteAllScanCells
- placeDesign
-
- # Netlist
- saveNetlist $::env(PNR_NET_DIR)/${DESIGN}.place.v
- write_sdf -version 2.1 -target_application verilog -interconn noport \
- $::env(PNR_NET_DIR)/${DESIGN}.place.sdf
-}
-
-#-----------------------------------------------------------------------------
-# ARBRE D'HORLOGE
-#-----------------------------------------------------------------------------
-if { $DO_CTS } {
-
- set_ccopt_property buffer_cells \
- [list CLKBUFX20 CLKBUFX16 CLKBUFX12 CLKBUFX8 CLKBUFX6 CLKBUFX4 CLKBUFX3 CLKBUFX2]
-
- set_ccopt_property inverter_cells \
- [list CLKINVX20 CLKINVX6 CLKINVX8 CLKINVX16 CLKINVX12 CLKINVX4 CLKINVX3 CLKINVX2 CLKINVX1]
-
- set_ccopt_property use_inverters true
-
- # Synthèse de l'arbre d'horloge
- optDesign -preCTS -outDir ${OPT_DIR}
- ccopt_design -cts -outDir ${OPT_DIR}
- optDesign -postCTS -outDir ${OPT_DIR}
-
- # Timing
- timeDesign -postCTS -outDir ${TIM_DIR}
-
- # Netlist
- saveNetlist $::env(PNR_NET_DIR)/${DESIGN}.cts.v
- write_sdf -version 2.1 -target_application verilog -interconn noport \
- $::env(PNR_NET_DIR)/${DESIGN}.cts.sdf
-}
-
-#-----------------------------------------------------------------------------
-# ROUTE
-#-----------------------------------------------------------------------------
-if { $DO_ROUTE } {
-
- # Ajout des filler cells
- addFiller -cell FILL32 FILL16 FILL8 FILL4 FILL2 FILL1 -prefix FILLER
-
- # Routage timing- et signal-integrity- driven
- setNanoRouteMode -routeWithTimingDriven true
- setNanoRouteMode -routeWithSIDriven true
- routeDesign -GlobalDetail
-
- # Extraction des capacités parasites
- setExtractRCMode -engine postRoute
- extractRC
-
- # Optimisations post-route
- setAnalysisMode -analysisType onChipVariation
- setAnalysisMode -cppr both
- optDesign -postRoute -setup -hold -outDir ${OPT_DIR}
-
- # Verifications physiques
- set_verify_drc_mode -report $::env(PNR_REP_DIR)/${DESIGN}.drc.rpt
- verify_drc
- verifyConnectivity -type all -error 1000 -warning 50 -report $::env(PNR_REP_DIR)/${DESIGN}.con.rpt
-
- # Timing
- timeDesign -postRoute -outDir ${TIM_DIR}
- report_timing > $::env(PNR_REP_DIR)/${DESIGN}.timing.rpt
-
- # Netlist
- saveNetlist $::env(PNR_NET_DIR)/${DESIGN}.route.v
- write_sdf -version 2.1 -target_application verilog -interconn noport \
- $::env(PNR_NET_DIR)/${DESIGN}.route.sdf
-}
-
-#-----------------------------------------------------------------------------
-# SAUVEGARDES
-#-----------------------------------------------------------------------------
-if { $DO_SAVE } {
-
- cd $::env(PNR_DIR)
-
- if {! [file isdirectory $OA_DIR] } {
- createLib $OA_DIR -attachTech gsclib045_tech
- }
- saveDesign -cellview "$OA_DIR $DESIGN layout"
-
- cd ../
-}
diff --git a/scripts/pwr.tcl b/scripts/pwr.tcl
deleted file mode 100644
index 963db0f..0000000
--- a/scripts/pwr.tcl
+++ /dev/null
@@ -1,107 +0,0 @@
-#-----------------------------------------------------------------------------
-# Project Tutoriels - Conception de circuits intégrés numériques
-#-----------------------------------------------------------------------------
-# File pwr.tcl
-# Authors Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
-# Lab GRM - Polytechnique Montréal
-# Date <2019-10-02 Wed>
-#-----------------------------------------------------------------------------
-# Brief Estimation du puissance du compteur BCD avec Voltus
-# Usage source setup.csh && cd implementation/pnr
-# voltus -files ../scripts/pwr.tcl
-#-----------------------------------------------------------------------------
-package require Tcl 8.5
-
-if { ![info exist ::env(PROJECT_HOME)] } {
- error "ERREUR: Configurer l'environnement (source setup.csh) avant d'utiliser ce script"
-}
-
-#-----------------------------------------------------------------------------
-# CONFIG
-#-----------------------------------------------------------------------------
-set DO_INIT 1
-set DO_STAT 1
-set DO_DYN 0
-
-set DESIGN compteur
-set OA compteur_oa
-set DUT compteur_tb/dut
-set PERIOD 1250ps
-set RESOLUTION 100ps
-set VCD_START 0ps
-set VCD_END 54375ps
-
-#-----------------------------------------------------------------------------
-# INIT
-#-----------------------------------------------------------------------------
-if { $DO_INIT } {
-
- cd $::env(PNR_DIR)
-
- # Unités par défaut
- set_time_unit -picoseconds
-
- # Importation du layout
- read_design -cellview "$OA $DESIGN layout" -physical_data
-
- # Mise à jour du timing à partir du mmmc
- set_analysis_view -update_timing
-
- # Configuration
- set_pg_library_mode -extraction_tech_file $::env(BE_QRC_LIB)/gpdk045.tch -celltype techonly \
- -power_pins {VDD 1.1} -ground_pins VSS \
- -decap_cells DECAP* -filler_cells FILL* \
-
- generate_pg_library -output $::env(PNR_REP_DIR)/power
- cd ../
-}
-
-#-----------------------------------------------------------------------------
-# ANALYSE STATIQUE
-#-----------------------------------------------------------------------------
-if { $DO_STAT } {
-
- set rep ${DESIGN}.stat
-
- # Configuration statique
- set_power_analysis_mode -reset
- set_power_analysis_mode -method static \
- -corner max \
- -create_binary_db false \
- -write_static_currents false
-
- # Activité moyenne
- set_default_switching_activity -reset
- set_default_switching_activity -input_activity 0.2 -period $PERIOD
-}
-
-#-----------------------------------------------------------------------------
-# ANALYSE DYNAMIQUE
-#-----------------------------------------------------------------------------
-if { $DO_DYN } {
-
- set rep ${DESIGN}.dyn
-
- # Configuration dynamique
- set_power_analysis_mode -reset
- set_power_analysis_mode -method dynamic_vectorbased \
- -enable_rtl_vectorbased_dynamic_analysis true \
- -power_grid_library $::env(PNR_REP_DIR)/power/techonly.cl \
- -corner max \
- -report_stat true \
- -create_binary_db true \
- -write_static_currents true \
- -report_missing_flop_outputs false
-
- # Activité issue du fichier VCD
- set_default_switching_activity -reset
- read_activity_file -reset
- read_activity_file -format VCD $::env(SIM_DIR)/pnr/${DESIGN}.vcd \
- -scope $DUT -start $VCD_START -end $VCD_END
-
- set_dynamic_power_simulation -resolution $RESOLUTION
-}
-
-# Report power
-report_power -format detailed -report_prefix $rep -output $::env(PNR_REP_DIR)/power
-file copy -force $::env(PNR_REP_DIR)/power/${rep}.rpt $::env(PNR_REP_DIR)/${rep}.rpt
diff --git a/scripts/sim.tcl b/scripts/sim.tcl
deleted file mode 100644
index d98acba..0000000
--- a/scripts/sim.tcl
+++ /dev/null
@@ -1,91 +0,0 @@
-#-----------------------------------------------------------------------------
-# Project : Tutoriels - Conception de circuits intégrés numériques
-#-----------------------------------------------------------------------------
-# File : sim.tcl
-# Authors : Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
-# Lab : GRM - Polytechnique Montréal
-# Date : <2019-07-24 Wed>
-#-----------------------------------------------------------------------------
-# Description: Script pour les simulations du compteur BCD avec Modelsim
-# HOW-TO : source setup.csh && cd simulation/
-# : (CLI) > vsim -c -do ${SCRIPTS_DIR}/sim.tcl
-# : (GUI) > vsim -do ${SCRIPTS_DIR}/sim.tcl
-#-----------------------------------------------------------------------------
-package require Tcl 8.5
-
-if { ![info exist ::env(PROJECT_HOME)] } {
- error "ERREUR: Configurer l'environnement (source setup.csh) avant d'utiliser ce script"
-}
-
-#-----------------------------------------------------------------------------
-# CONFIG
-#-----------------------------------------------------------------------------
-set DO_BEH 0; # Modèle comportemental
-set DO_SYN 0; # Netlist post-synthèse
-set DO_PNR 1; # Netlist post-placement-routage
-set DO_SIM 1; # 0=Compilation; 1=Compilation + Simulation
-set DO_VCD 1; # Sauvegarde de l'activité au format VCD
-
-set top compteur
-set tb compteur_tb
-set dut dut
-set work work
-set lib gpdk45
-
-if { $DO_BEH } { set workD $::env(SIM_DIR)/beh }
-if { $DO_SYN } { set workD $::env(SIM_DIR)/syn }
-if { $DO_PNR } { set workD $::env(SIM_DIR)/pnr }
-
-set log ${workD}/${top}.log
-set wlf ${workD}/${top}.wlf
-set vcd ${workD}/${top}.vcd
-set wave ${workD}/${top}.wave.do
-
-if { $DO_SYN } { set net $::env(SYN_NET_DIR)/${top}.syn }
-if { $DO_PNR } { set net $::env(PNR_NET_DIR)/${top}.route }
-
-#-----------------------------------------------------------------------------
-# COMPILATION
-#-----------------------------------------------------------------------------
-
-# Création du répertoire de travail
-if { ![file exist $workD] } {
- file mkdir $workD
-}
-
-# Mise à jour du modelsim.ini avec les librairies GPDK45
-if { [file exist "./modelsim.ini"] } {
- file delete "./modelsim.ini"
-}
-vmap -c
-vmap $lib $::env(KIT_SIMLIB)/gsclib045_slow
-
-# Work
-if { [file exist ${workD}/${work}] } {
- vdel -all -lib ${workD}/${work}
-}
-vlib ${workD}/${work}
-vmap ${work} ${workD}/${work}
-
-# Model
-if { $DO_BEH } {
- vcom -2008 -work $work $::env(SRC_DIR)/${top}.vhd
- vcom -2008 -work $work $::env(SRC_DIR)/${tb}.vhd
-
-# Netlist
-} elseif { $DO_SYN || $DO_PNR } {
- vlog -work $work ${net}.v
- vcom -2008 -work $work $::env(SRC_DIR)/${tb}.vhd
-}
-
-#-----------------------------------------------------------------------------
-# SIMULATION
-#-----------------------------------------------------------------------------
-
-if { $DO_SIM && $DO_BEH } {
- vsim -c -t ps -voptargs=+acc -do run.do -logfile $log -wlf $wlf ${work}.${tb}
-}
-
-if { $DO_SIM && ($DO_SYN || $DO_PNR) } {
- vsim -c -t ps -voptargs=+acc -do run.do -logfile $log -wlf $wlf -L $lib -sdfmax ${dut}=${net}.sdf ${work}.${tb}
-}
diff --git a/scripts/syn.tcl b/scripts/syn.tcl
deleted file mode 100644
index 1989c51..0000000
--- a/scripts/syn.tcl
+++ /dev/null
@@ -1,142 +0,0 @@
-#-----------------------------------------------------------------------------
-# Project Tutoriels - Conception de circuits intégrés numériques
-#-----------------------------------------------------------------------------
-# File syn.tcl
-# Author Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
-# Lab GRM - Polytechnique Montreal
-# Date <2019-10-01 Tue>
-#-----------------------------------------------------------------------------
-# Brief Synthèse du compteur avec Genus
-# Usage cd implementation
-# genus -files ../scripts/syn.tcl
-#-----------------------------------------------------------------------------
-package require Tcl 8.5
-
-if { ![info exist ::env(PROJECT_HOME)] } {
- error "ERREUR: Configurer l'environnement (source setup.csh) avant d'utiliser ce script"
-}
-
-#-----------------------------------------------------------------------------
-# CONFIG
-#-----------------------------------------------------------------------------
-set DO_INIT 1
-set DO_ELAB 1
-set DO_SDC 1
-set DO_SYN 1
-set DO_REPORTS 1
-
-set DESIGN compteur; # Top-level
-set SYN_EFFORT high; # low | medium | high | express
-
-# Create directories if they do not exists
-file mkdir $::env(SYN_REP_DIR) $::env(SYN_NET_DIR)
-
-#-----------------------------------------------------------------------------
-# CONFIG
-#-----------------------------------------------------------------------------
-set DO_INIT 1
-set DO_ELAB 1
-set DO_SDC 1
-set DO_SYN 1
-
-set DESIGN compteur; # Top-level
-set SYN_EFFORT high; # low | medium | high | express
-
-# Création des répertoires de destination
-file mkdir $::env(SYN_REP_DIR) $::env(SYN_NET_DIR)
-
-#-----------------------------------------------------------------------------
-# SAVE
-#-----------------------------------------------------------------------------
-proc save { basename } {
- report_timing > $::env(SYN_REP_DIR)/${basename}.timing.rpt
- report_area > $::env(SYN_REP_DIR)/${basename}.area.rpt
- report_gates > $::env(SYN_REP_DIR)/${basename}.gates.rpt
- report_power > $::env(SYN_REP_DIR)/${basename}.power.rpt
-}
-
-#-----------------------------------------------------------------------------
-# INIT
-#-----------------------------------------------------------------------------
-if { $DO_INIT } {
-
- # Paramètres
- set_db information_level 11; # Verbosité: 1-11
- set_db max_cpus_per_server 8; # Numbre max de thread utilisable
- set_db hdl_vhdl_read_version 2008; # Standard VHDL
- set_db hdl_error_on_blackbox true; # Éviter les black-box
- set_db hdl_error_on_latch true; # Éviter les latch
-
- set_db init_hdl_search_path [list $::env(SRC_DIR)]
- set_db init_lib_search_path [list $::env(FE_TIM_LIB) \
- $::env(BE_LEF_LIB) \
- $::env(BE_QRC_LIB)]
-
- # Librairies de timing: max=setup, min=hold
- read_libs -max_libs slow_vdd1v0_basicCells.lib -min_libs fast_vdd1v0_basicCells.lib
-
- # Libraries physiques: stdcells + interconnect
- read_physical -lef gsclib045_tech.lef
- read_qrc gpdk045.tch
- set_db interconnect_mode ple; # wireload | ple (Physical Layout Estimators)
-}
-
-#-----------------------------------------------------------------------------
-# ELABORATION
-#-----------------------------------------------------------------------------
-if { $DO_ELAB } {
-
- # Compilation
- read_hdl -vhdl [list compteur.vhd]
-
- # Conserver les compteurs de performance
- set_db hdl_preserve_unused_flop true
-
- # Élaboration
- elaborate $DESIGN
-
- # Rapports
- check_design -all > $::env(SYN_REP_DIR)/${DESIGN}.check.rpt
- report_module -depth 3 > $::env(SYN_REP_DIR)/${DESIGN}.hier_elab.rpt
- write_hdl > $::env(SYN_NET_DIR)/${DESIGN}.elab.v
-}
-
-#-----------------------------------------------------------------------------
-# CONTRAINTES
-#-----------------------------------------------------------------------------
-if { $DO_SDC } {
-
- # Contraintes de timing
- read_sdc $::env(CONST_DIR)/timing.sdc
-
- # Rapports
- report_timing -lint -verbose > $::env(SYN_REP_DIR)/${DESIGN}.timing_lint.rpt
- report_clocks > $::env(SYN_REP_DIR)/${DESIGN}.clk.rpt
- report_clocks -generated >> $::env(SYN_REP_DIR)/${DESIGN}.clk.rpt
-}
-
-#-----------------------------------------------------------------------------
-# SYNTHÈSE
-#-----------------------------------------------------------------------------
-if { $DO_SYN } {
-
- # Synthèse générique
- set_db syn_generic_effort $SYN_EFFORT
- syn_generic ${DESIGN}
- save ${DESIGN}.gen
-
- # Map
- set_db syn_map_effort $SYN_EFFORT
- syn_map ${DESIGN}
- save ${DESIGN}.map
-
- # Optimisations
- set_db syn_opt_effort $SYN_EFFORT
- syn_opt ${DESIGN}
- save ${DESIGN}.syn
-
- # Netlist
- write_sdc > $::env(CONST_DIR)/${DESIGN}.syn.sdc
- write_hdl > $::env(SYN_NET_DIR)/${DESIGN}.syn.v
- write_sdf -nonegchecks -setuphold split -version 2.1 > $::env(SYN_NET_DIR)/${DESIGN}.syn.sdf
-}
diff --git a/simulation/run.do b/simulation/run.do
deleted file mode 100644
index 3979db8..0000000
--- a/simulation/run.do
+++ /dev/null
@@ -1,23 +0,0 @@
-global DO_VCD
-global tb
-global dut
-global vcd
-
-set StdArithNoWarnings 1
-set NumericStdNoWarnings 1
-
-onerror { break }
-onbreak {
- if { $DO_VCD } { vcd flush }
- quit -f
-}
-
-log * -r
-add wave -r /*
-
-if { $DO_VCD } {
- vcd file $vcd
- vcd add -r /${tb}/${dut}/*
-}
-
-run -all
--
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