diff --git a/compteur/constraints/compteur.syn.sdc b/compteur/constraints/compteur.syn.sdc
new file mode 100644
index 0000000000000000000000000000000000000000..e285f8a8151719730216e9b44d49672848245ba3
--- /dev/null
+++ b/compteur/constraints/compteur.syn.sdc
@@ -0,0 +1,35 @@
+# ####################################################################
+
+# Created by Genus(TM) Synthesis Solution 18.10-p003_1 on Wed Oct 02 14:33:08 EDT 2019
+
+# ####################################################################
+
+set sdc_version 2.0
+
+set_units -capacitance 1000.0fF
+set_units -time 1000.0ps
+
+# Set the current design
+current_design compteur
+
+create_clock -name "clk" -period 1.25 -waveform {0.0 0.625} [get_ports i_clk]
+set_load -pin_load -max 0.5 [get_ports {o_cnt[3]}]
+set_load -pin_load -max 0.5 [get_ports {o_cnt[2]}]
+set_load -pin_load -max 0.5 [get_ports {o_cnt[1]}]
+set_load -pin_load -max 0.5 [get_ports {o_cnt[0]}]
+set_false_path -from [get_ports i_rstn]
+set_clock_gating_check -setup 0.0
+set_input_delay -clock [get_clocks clk] -add_delay 0.2 [get_ports i_clk]
+set_input_delay -clock [get_clocks clk] -add_delay 0.2 [get_ports i_rstn]
+set_input_delay -clock [get_clocks clk] -add_delay 0.2 [get_ports i_en]
+set_output_delay -clock [get_clocks clk] -add_delay 0.2 [get_ports {o_cnt[3]}]
+set_output_delay -clock [get_clocks clk] -add_delay 0.2 [get_ports {o_cnt[2]}]
+set_output_delay -clock [get_clocks clk] -add_delay 0.2 [get_ports {o_cnt[1]}]
+set_output_delay -clock [get_clocks clk] -add_delay 0.2 [get_ports {o_cnt[0]}]
+set_driving_cell -lib_cell BUFX20 -library slow_vdd1v0 -pin "Y" [get_ports i_clk]
+set_driving_cell -lib_cell BUFX20 -library slow_vdd1v0 -pin "Y" [get_ports i_rstn]
+set_driving_cell -lib_cell BUFX20 -library slow_vdd1v0 -pin "Y" [get_ports i_en]
+set_ideal_network [get_pins {rstn_sync_reg[1]/Q}]
+set_dont_use [get_lib_cells slow_vdd1v0/HOLDX1]
+set_clock_uncertainty -setup 0.1 [get_clocks clk]
+set_clock_uncertainty -hold 0.03 [get_clocks clk]
diff --git a/compteur/constraints/mmmc.tcl b/compteur/constraints/mmmc.tcl
index 4c37e84ee79f19a31e03ec97620abf9a2b5d4e78..865702b66fea51012a71d994846417d515e43f83 100644
--- a/compteur/constraints/mmmc.tcl
+++ b/compteur/constraints/mmmc.tcl
@@ -1,32 +1,37 @@
#-----------------------------------------------------------------------------
-# Project : Tutoriels - Conception de circuits intégrés numériques
+# Project Tutoriels - Conception de circuits intégrés numériques
#-----------------------------------------------------------------------------
-# File : mmmc.tcl
-# Authors : Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
-# Lab : GRM - Polytechnique Montréal
-# Date : <2019-07-24 Wed>
+# File mmmc.tcl
+# Author Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
+# Lab GRM - Polytechnique Montreal
+# Date <2019-09-10 Tue>
#-----------------------------------------------------------------------------
-# Description: Fichier de configuration "Multi-Mode Multi-Corner"
-# pour le placement et routage du compteur BCD
+# Brief Configuration Multi-Mode Multi-Corner
#-----------------------------------------------------------------------------
-set fastlib $::env(FE_TIM_LIB)/fast_vdd1v0_basicCells.lib
+# constraint mode
+create_constraint_mode -name const -sdc_files $::env(CONST_DIR)/${DESIGN}.syn.sdc
+
+# rc corner
+create_rc_corner -name rc -qx_tech_file $::env(BE_QRC_LIB)/gpdk045.tch
+
+# Libraries
+set fast_lib $::env(FE_TIM_LIB)/fast_vdd1v0_basicCells.lib
+set slow_lib $::env(FE_TIM_LIB)/slow_vdd1v0_basicCells.lib
# operating conditions
-create_op_cond -name pvt_fast -P 1.0 -V 1.0 -T 25.0 -library_file $fastlib
+create_op_cond -name fast_opcond -P 1.0 -V 1.0 -T 0 -library_file $fast_lib
+create_op_cond -name slow_opcond -P 1.0 -V 0.9 -T 125.0 -library_file $slow_lib
# library sets
-create_library_set -name libs_fast -timing $fastlib -si $::env(BE_CDB_LIB)/fast.cdb
-
-# rc corner
-create_rc_corner -name rc_basic -qx_tech_file $::env(BE_QRC_LIB)/gpdk045.tch
+create_library_set -name fast_libset -timing $fast_lib -si $::env(BE_CDB_LIB)/fast.cdb
+create_library_set -name slow_libset -timing $slow_lib -si $::env(BE_CDB_LIB)/slow.cdb
# delay corner
-create_delay_corner -name fast_basic -library_set libs_fast -rc_corner rc_basic
-
-# constraint mode
-create_constraint_mode -name const_mode -sdc_files $::env(CONST_DIR)/${DESIGN}.syn.sdc
+create_delay_corner -name fast_corner -library_set fast_libset -rc_corner rc
+create_delay_corner -name slow_corner -library_set slow_libset -rc_corner rc
# analysis view
-create_analysis_view -name av_fast -constraint_mode const_mode -delay_corner fast_basic
-set_analysis_view -setup av_fast -hold av_fast
+create_analysis_view -name fast_av -constraint_mode const -delay_corner fast_corner
+create_analysis_view -name slow_av -constraint_mode const -delay_corner slow_corner
+set_analysis_view -setup slow_av -hold fast_av
diff --git a/compteur/constraints/timing.sdc b/compteur/constraints/timing.sdc
index b3d3f9252cae84793c1bc86c1f9f3735b25e95f6..9acdcb873b0b7027c29669541f9ff2c33fc01d21 100644
--- a/compteur/constraints/timing.sdc
+++ b/compteur/constraints/timing.sdc
@@ -1,12 +1,12 @@
#-----------------------------------------------------------------------------
-# Project : Tutoriels - Conception de circuits intégrés numériques
+# Project Tutoriels - Conception de circuits intégrés numériques
#-----------------------------------------------------------------------------
-# File : timing.sdc
-# Authors : Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
-# Lab : GRM - Polytechnique Montréal
-# Date : <2019-07-24 Wed>
+# File timing.sdc
+# Authors Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
+# Lab GRM - Polytechnique Montréal
+# Date <2019-10-02 Wed>
#-----------------------------------------------------------------------------
-# Description: Fichier de contraintes
+# Brief Contraintes de timing
#-----------------------------------------------------------------------------
# Unités par défaut
@@ -14,20 +14,24 @@ set_time_unit -picoseconds
set_load_unit -femtofarads
# Point de fonctionnement
-set_db / .operating_conditions PVT_1P1V_0C
+set_operating_conditions -max PVT_1P1V_0C -min PVT_0P9V_125C; # 1.1V, OC ; 0.9V, 125C
-# Horloge principale: 1GHz
+# Horloge principale
set clk "clk"
-create_clock -period 1000 -name $clk [get_ports i_clk]
+create_clock -period 1250 -name $clk [get_ports i_clk]
-# Incertitudes sur l'horloge: setup = 100ps, hold = 30ps
+# Incertitudes sur l'horloge: setup = 100ps, hold = 30ps
set_db [get_clocks $clk] .clock_setup_uncertainty 100
set_db [get_clocks $clk] .clock_hold_uncertainty 30
+# Reset
+set_false_path -from [get_ports i_rstn]
+set_ideal_network [get_nets rstn_sync\[1\]]
+
# Entrées
-set_input_delay 300 -clock [get_clocks $clk] [all_inputs]
+set_input_delay 200 -clock [get_clocks $clk] [all_inputs]
set_db [all_inputs] .external_driver [vfind [vfind / -libcell BUFX20] -libpin Y]
# Sorties
-set_output_delay 300 -clock [get_clocks $clk] [all_outputs]
-set_db [all_outputs] .external_pin_cap 1000
+set_output_delay 200 -clock [get_clocks $clk] [all_outputs]
+set_db [all_outputs] .external_pin_cap 500
diff --git a/compteur/implementation/.gitignore b/compteur/implementation/.gitignore
new file mode 100644
index 0000000000000000000000000000000000000000..b4193518768a1eef39b2da7835bad5e9742d1303
--- /dev/null
+++ b/compteur/implementation/.gitignore
@@ -0,0 +1,16 @@
+*.cmd
+*.log
+.lec*
+liboa/
+timingReports/
+.cadence/
+fv/
+pnr/lec/
+pnr/reports/cts/
+*.old
+preferred_layer_short_segment.rpt
+.rs*
+rc_model.bin
+opt/
+power/
+voltus_*
diff --git a/compteur/implementation/.powerAnalysis.pinfo b/compteur/implementation/.powerAnalysis.pinfo
new file mode 100644
index 0000000000000000000000000000000000000000..9c69656eda7d734e3122b60032baea8728695b72
--- /dev/null
+++ b/compteur/implementation/.powerAnalysis.pinfo
@@ -0,0 +1,8 @@
+
+Hostname pcys41
+
+Wall clock 7.436569
+
+CPU time 6.426093
+
+Peak memory (process): 535609344
diff --git a/compteur/implementation/cds.lib b/compteur/implementation/cds.lib
new file mode 100644
index 0000000000000000000000000000000000000000..b489764c15c12d492f0a8c04bbec5fe28a31c593
--- /dev/null
+++ b/compteur/implementation/cds.lib
@@ -0,0 +1,15 @@
+#-----------------------------------------------------------------------------
+# Project Tutoriels - Conception de circuits intégrés numériques
+#-----------------------------------------------------------------------------
+# File cds.lib
+# Authors Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
+# Lab GRM - Polytechnique Montréal
+# Date <2019-10-02 Wed>
+#-----------------------------------------------------------------------------
+# Brief Configuration des librairies pour les outils Cadence
+#-----------------------------------------------------------------------------
+DEFINE gpdk045 ${KIT_GPDK}/gpdk045
+DEFINE gsclib045_tech ${KIT_SCLIB}/gsclib045_tech/oa22/gsclib045_tech
+DEFINE gsclib045 ${KIT_SCLIB}/gsclib045/oa22/gsclib045
+DEFINE giolib045 ${KIT_IOLIB}/giolib045/oa22/giolib045
+DEFINE liboa liboa
diff --git a/compteur/implementation/pnr/.gitignore b/compteur/implementation/pnr/.gitignore
deleted file mode 100644
index cfc93770aa0858c9541487731d87e8919bba6883..0000000000000000000000000000000000000000
--- a/compteur/implementation/pnr/.gitignore
+++ /dev/null
@@ -1,11 +0,0 @@
-*~
-*.log
-*.cmd
-*.old
-*.setpower
-.powerAnalysis.pinfo
-preferred_layer_short_segment.rpt
-.cadence/
-liboa/
-reports/cts/
-reports/power/
diff --git a/compteur/implementation/pnr/cds.lib b/compteur/implementation/pnr/cds.lib
deleted file mode 100644
index 7dc594c3d589b57feb0b86354e579b5b2e4ef65b..0000000000000000000000000000000000000000
--- a/compteur/implementation/pnr/cds.lib
+++ /dev/null
@@ -1,15 +0,0 @@
-#-----------------------------------------------------------------------------
-# Project : Tutoriels - Conception de circuits intégrés numériques
-#-----------------------------------------------------------------------------
-# File : cds.lib
-# Authors : Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
-# Lab : GRM - Polytechnique Montréal
-# Date : <2019-07-24 Wed>
-#-----------------------------------------------------------------------------
-# Description: Configuration des librairies pour les outils Cadence
-#-----------------------------------------------------------------------------
-DEFINE gpdk045 ${KIT_GPDK}/gpdk045
-DEFINE gsclib045_tech ${KIT_SCLIB}/gsclib045_tech/oa22/gsclib045_tech
-DEFINE gsclib045 ${KIT_SCLIB}/gsclib045/oa22/gsclib045
-DEFINE giolib045 ${KIT_IOLIB}/giolib045/oa22/giolib045
-DEFINE liboa liboa
diff --git a/compteur/implementation/pnr/netlist/compteur.cts.sdf b/compteur/implementation/pnr/netlist/compteur.cts.sdf
new file mode 100644
index 0000000000000000000000000000000000000000..016704744756295be33250bcbeb49e4b38e9feac
--- /dev/null
+++ b/compteur/implementation/pnr/netlist/compteur.cts.sdf
@@ -0,0 +1,375 @@
+(DELAYFILE
+ (SDFVERSION "2.1")
+ (DESIGN "compteur")
+ (DATE "Wed Oct 2 14:38:45 2019")
+ (VENDOR "Cadence Design Systems, Inc.")
+ (PROGRAM "Innovus")
+ (VERSION "v18.10-p002_1 ((64bit) 05/29/2018 19:19 (Linux 2.6.18-194.el5))")
+ (DIVIDER /)
+ (VOLTAGE 0.900000::0.900000)
+ (PROCESS "1.000000::1.000000")
+ (TEMPERATURE 125.000000::125.000000)
+ (TIMESCALE 1.0 ns)
+
+ (CELL
+ (CELLTYPE "compteur")
+ (INSTANCE)
+ (DELAY
+ (ABSOLUTE
+ (INTERCONNECT cnt_reg\[0\]/Q g345__9682/A1N (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT cnt_reg\[0\]/Q g347__1309/B (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT cnt_reg\[0\]/Q FE_OFC26_FE_OFN8_o_cnt_0/A (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT FE_OFC7_o_cnt_1/Y g342__3772/A0 (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT FE_OFC22_FE_OFN5_o_cnt_1/Y FE_OFC7_o_cnt_1/A (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT cnt_reg\[1\]/Q g339__4296/B0 (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT cnt_reg\[1\]/Q g344__4547/A (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT cnt_reg\[1\]/Q cnt_reg\[1\]/D (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT cnt_reg\[1\]/Q g343__1474/A (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT cnt_reg\[1\]/Q FE_OFC22_FE_OFN5_o_cnt_1/A (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT cnt_reg\[1\]/Q FE_OFC23_FE_OFN5_o_cnt_1/A (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT FE_OFC20_FE_OFN3_o_cnt_2/Y FE_OFC21_FE_OFN3_o_cnt_2/A (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT FE_OFC20_FE_OFN3_o_cnt_2/Y g337__8780/A1 (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT FE_OFC20_FE_OFN3_o_cnt_2/Y g346__2683/A (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT FE_OFC20_FE_OFN3_o_cnt_2/Y g342__3772/A1 (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT cnt_reg\[2\]/Q cnt_reg\[2\]/SE (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT cnt_reg\[2\]/Q FE_OFC20_FE_OFN3_o_cnt_2/A (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT FE_OFC1_o_cnt_3/Y g339__4296/A0 (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT FE_OFC24_FE_OFN0_o_cnt_3/Y FE_OFC1_o_cnt_3/A (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT cnt_reg\[3\]/Q g337__8780/A0 (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT cnt_reg\[3\]/Q g346__2683/B (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT cnt_reg\[3\]/Q FE_OFC24_FE_OFN0_o_cnt_3/A (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT cnt_reg\[3\]/Q FE_OFC25_FE_OFN0_o_cnt_3/A (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT rstn_sync_reg\[1\]/Q cnt_reg\[3\]/RN (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT rstn_sync_reg\[1\]/Q cnt_reg\[2\]/RN (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT rstn_sync_reg\[1\]/Q cnt_reg\[1\]/RN (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT rstn_sync_reg\[1\]/Q cnt_reg\[0\]/RN (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT rstn_sync_reg\[0\]/Q rstn_sync_reg\[1\]/D (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g347__1309/Y cnt_reg\[1\]/SE (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g347__1309/Y g342__3772/B0 (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g347__1309/Y g343__1474/B (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g347__1309/Y g345__9682/B0 (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g346__2683/Y g339__4296/B1 (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g346__2683/Y g344__4547/B (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g345__9682/Y cnt_reg\[0\]/D (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g344__4547/Y cnt_reg\[1\]/SI (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g342__3772/Y g339__4296/A1 (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT FE_OFC27_n_7/Y cnt_reg\[2\]/D (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g343__1474/Y g337__8780/A2 (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g343__1474/Y cnt_reg\[2\]/SI (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g343__1474/Y FE_OFC27_n_7/A (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g339__4296/Y g337__8780/B0 (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g337__8780/Y cnt_reg\[3\]/D (0.000::0.000) (0.000::0.000))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "INVX1")
+ (INSTANCE FE_OFC27_n_7)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (0.118::0.118) (0.072::0.072))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "CLKBUFX20")
+ (INSTANCE FE_OFC26_FE_OFN8_o_cnt_0)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (0.399::0.399) (0.473::0.473))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "CLKBUFX20")
+ (INSTANCE FE_OFC25_FE_OFN0_o_cnt_3)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (0.406::0.406) (0.480::0.480))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "INVX1")
+ (INSTANCE FE_OFC24_FE_OFN0_o_cnt_3)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (0.070::0.070) (0.072::0.072))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "CLKBUFX20")
+ (INSTANCE FE_OFC23_FE_OFN5_o_cnt_1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (0.423::0.423) (0.497::0.497))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "INVX1")
+ (INSTANCE FE_OFC22_FE_OFN5_o_cnt_1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (0.090::0.090) (0.091::0.091))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "CLKINVX20")
+ (INSTANCE FE_OFC21_FE_OFN3_o_cnt_2)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (0.374::0.374) (0.454::0.454))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "INVX2")
+ (INSTANCE FE_OFC20_FE_OFN3_o_cnt_2)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (0.094::0.094) (0.100::0.100))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "INVX1")
+ (INSTANCE FE_OFC7_o_cnt_1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (0.041::0.041) (0.044::0.044))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "INVX1")
+ (INSTANCE FE_OFC1_o_cnt_3)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (0.035::0.035) (0.037::0.037))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "DFFRHQX1")
+ (INSTANCE rstn_sync_reg\[1\])
+ (DELAY
+ (ABSOLUTE
+ (IOPATH RN Q () (0.072::0.072))
+ (IOPATH CK Q (0.243::0.243) (0.213::0.213))
+ )
+ )
+ (TIMINGCHECK
+ (WIDTH (negedge RN) (::0.135))
+ (SETUPHOLD (posedge D) (posedge CK) (::0.114) (::-0.067))
+ (SETUPHOLD (negedge D) (posedge CK) (::0.047) (::0.025))
+ (WIDTH (posedge CK) (::0.152))
+ (WIDTH (negedge CK) (::0.165))
+ )
+ )
+
+ (CELL
+ (CELLTYPE "DFFRHQX1")
+ (INSTANCE rstn_sync_reg\[0\])
+ (DELAY
+ (ABSOLUTE
+ (IOPATH RN Q () (0.080::0.080))
+ (IOPATH CK Q (0.250::0.250) (0.222::0.222))
+ )
+ )
+ (TIMINGCHECK
+ (WIDTH (negedge RN) (::0.135))
+ (SETUPHOLD (posedge D) (posedge CK) (::0.100) (::-0.054))
+ (SETUPHOLD (negedge D) (posedge CK) (::0.034) (::0.036))
+ (WIDTH (posedge CK) (::0.152))
+ (WIDTH (negedge CK) (::0.165))
+ )
+ )
+
+ (CELL
+ (CELLTYPE "DFFRHQX1")
+ (INSTANCE cnt_reg\[3\])
+ (DELAY
+ (ABSOLUTE
+ (IOPATH RN Q () (0.109::0.109))
+ (IOPATH CK Q (0.285::0.285) (0.260::0.260))
+ )
+ )
+ (TIMINGCHECK
+ (WIDTH (negedge RN) (::0.081))
+ (SETUPHOLD (posedge D) (posedge CK) (::0.154) (::-0.106))
+ (SETUPHOLD (negedge D) (posedge CK) (::0.076) (::-0.000))
+ (WIDTH (posedge CK) (::0.152))
+ (WIDTH (negedge CK) (::0.165))
+ )
+ )
+
+ (CELL
+ (CELLTYPE "SDFFRHQX1")
+ (INSTANCE cnt_reg\[2\])
+ (DELAY
+ (ABSOLUTE
+ (IOPATH RN Q () (0.087::0.087))
+ (IOPATH CK Q (0.265::0.265) (0.238::0.238))
+ )
+ )
+ (TIMINGCHECK
+ (WIDTH (negedge RN) (::0.081))
+ (SETUPHOLD (posedge SI) (posedge CK) (::0.229) (::-0.168))
+ (SETUPHOLD (negedge SI) (posedge CK) (::0.200) (::-0.105))
+ (SETUPHOLD (posedge SE) (posedge CK) (::0.186) (::-0.066))
+ (SETUPHOLD (negedge SE) (posedge CK) (::0.218) (::-0.026))
+ (SETUPHOLD (posedge D) (posedge CK) (::0.210) (::-0.148))
+ (SETUPHOLD (negedge D) (posedge CK) (::0.129) (::-0.039))
+ (WIDTH (posedge CK) (::0.152))
+ (WIDTH (negedge CK) (::0.161))
+ )
+ )
+
+ (CELL
+ (CELLTYPE "OAI31X1")
+ (INSTANCE g337__8780)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A0 Y (0.156::0.156) (0.144::0.144))
+ (IOPATH A1 Y (0.162::0.162) (0.143::0.143))
+ (IOPATH A2 Y (0.167::0.167) (0.112::0.112))
+ (IOPATH B0 Y (0.080::0.080) (0.124::0.124))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "SDFFRHQX1")
+ (INSTANCE cnt_reg\[1\])
+ (DELAY
+ (ABSOLUTE
+ (IOPATH RN Q () (0.129::0.129))
+ (IOPATH CK Q (0.303::0.303) (0.279::0.279))
+ )
+ )
+ (TIMINGCHECK
+ (WIDTH (negedge RN) (::0.081))
+ (SETUPHOLD (posedge SI) (posedge CK) (::0.211) (::-0.150))
+ (SETUPHOLD (negedge SI) (posedge CK) (::0.140) (::-0.048))
+ (SETUPHOLD (posedge SE) (posedge CK) (::0.195) (::-0.074))
+ (SETUPHOLD (negedge SE) (posedge CK) (::0.226) (::-0.033))
+ (SETUPHOLD (posedge D) (posedge CK) (::0.248) (::-0.185))
+ (SETUPHOLD (negedge D) (posedge CK) (::0.174) (::-0.081))
+ (WIDTH (posedge CK) (::0.152))
+ (WIDTH (negedge CK) (::0.161))
+ )
+ )
+
+ (CELL
+ (CELLTYPE "AOI22X1")
+ (INSTANCE g339__4296)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A0 Y (0.090::0.090) (0.105::0.105))
+ (IOPATH A1 Y (0.112::0.112) (0.126::0.126))
+ (IOPATH B0 Y (0.127::0.127) (0.125::0.125))
+ (IOPATH B1 Y (0.068::0.068) (0.069::0.069))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "DFFRHQX1")
+ (INSTANCE cnt_reg\[0\])
+ (DELAY
+ (ABSOLUTE
+ (IOPATH RN Q () (0.102::0.102))
+ (IOPATH CK Q (0.279::0.279) (0.252::0.252))
+ )
+ )
+ (TIMINGCHECK
+ (WIDTH (negedge RN) (::0.081))
+ (SETUPHOLD (posedge D) (posedge CK) (::0.128) (::-0.081))
+ (SETUPHOLD (negedge D) (posedge CK) (::0.055) (::0.018))
+ (WIDTH (posedge CK) (::0.152))
+ (WIDTH (negedge CK) (::0.165))
+ )
+ )
+
+ (CELL
+ (CELLTYPE "OAI21X1")
+ (INSTANCE g342__3772)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A0 Y (0.075::0.075) (0.090::0.090))
+ (IOPATH A1 Y (0.118::0.118) (0.123::0.123))
+ (IOPATH B0 Y (0.062::0.062) (0.103::0.103))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "NAND2XL")
+ (INSTANCE g343__1474)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (0.128::0.128) (0.194::0.194))
+ (IOPATH B Y (0.090::0.090) (0.154::0.154))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "NOR2X1")
+ (INSTANCE g344__4547)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (0.113::0.113) (0.101::0.101))
+ (IOPATH B Y (0.056::0.056) (0.043::0.043))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "AOI2BB1X1")
+ (INSTANCE g345__9682)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A0N Y (0.097::0.097) (0.117::0.117))
+ (IOPATH A1N Y (0.112::0.112) (0.131::0.131))
+ (IOPATH B0 Y (0.087::0.087) (0.071::0.071))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "AND2X1")
+ (INSTANCE g346__2683)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (0.171::0.171) (0.120::0.120))
+ (IOPATH B Y (0.171::0.171) (0.112::0.112))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "AND2X1")
+ (INSTANCE g347__1309)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (0.148::0.148) (0.094::0.094))
+ (IOPATH B Y (0.183::0.183) (0.126::0.126))
+ )
+ )
+ )
+)
diff --git a/compteur/implementation/pnr/netlist/compteur.cts.v b/compteur/implementation/pnr/netlist/compteur.cts.v
new file mode 100644
index 0000000000000000000000000000000000000000..ad4d60622f8c8a7fd2367ca3675a4edd12bba876
--- /dev/null
+++ b/compteur/implementation/pnr/netlist/compteur.cts.v
@@ -0,0 +1,123 @@
+/*
+###############################################################
+# Generated by: Cadence Innovus 18.10-p002_1
+# OS: Linux x86_64(Host ID pcys41)
+# Generated on: Wed Oct 2 14:38:44 2019
+# Design: compteur
+# Command: saveNetlist /export/tmp/fiorentino/Projects/tutoriel_numerique/compteur/implementation/pnr/netlist/compteur.cts.v
+###############################################################
+*/
+// Generated by Cadence Genus(TM) Synthesis Solution 18.10-p003_1
+// Generated on: Oct 2 2019 14:33:08 EDT (Oct 2 2019 18:33:08 UTC)
+// Verification Directory fv/compteur
+module compteur (
+ i_clk,
+ i_rstn,
+ i_en,
+ o_cnt);
+ input i_clk;
+ input i_rstn;
+ input i_en;
+ output [3:0] o_cnt;
+
+ // Internal wires
+ wire FE_OFN8_o_cnt_0;
+ wire FE_OFN7_o_cnt_1;
+ wire FE_OFN6_o_cnt_1;
+ wire FE_OFN5_o_cnt_1;
+ wire FE_OFN4_o_cnt_2;
+ wire FE_OFN3_o_cnt_2;
+ wire FE_OFN2_o_cnt_3;
+ wire FE_OFN1_o_cnt_3;
+ wire FE_OFN0_o_cnt_3;
+ wire [1:0] rstn_sync;
+ wire n_1;
+ wire n_2;
+ wire n_3;
+ wire n_4;
+ wire n_5;
+ wire n_6;
+ wire n_7;
+ wire n_8;
+ wire n_9;
+
+ INVX1 FE_OFC27_n_7 (.Y(n_6),
+ .A(n_7));
+ CLKBUFX20 FE_OFC26_FE_OFN8_o_cnt_0 (.Y(o_cnt[0]),
+ .A(FE_OFN8_o_cnt_0));
+ CLKBUFX20 FE_OFC25_FE_OFN0_o_cnt_3 (.Y(o_cnt[3]),
+ .A(FE_OFN0_o_cnt_3));
+ INVX1 FE_OFC24_FE_OFN0_o_cnt_3 (.Y(FE_OFN1_o_cnt_3),
+ .A(FE_OFN0_o_cnt_3));
+ CLKBUFX20 FE_OFC23_FE_OFN5_o_cnt_1 (.Y(o_cnt[1]),
+ .A(FE_OFN5_o_cnt_1));
+ INVX1 FE_OFC22_FE_OFN5_o_cnt_1 (.Y(FE_OFN6_o_cnt_1),
+ .A(FE_OFN5_o_cnt_1));
+ CLKINVX20 FE_OFC21_FE_OFN3_o_cnt_2 (.Y(o_cnt[2]),
+ .A(FE_OFN4_o_cnt_2));
+ INVX2 FE_OFC20_FE_OFN3_o_cnt_2 (.Y(FE_OFN4_o_cnt_2),
+ .A(FE_OFN3_o_cnt_2));
+ INVX1 FE_OFC7_o_cnt_1 (.Y(FE_OFN7_o_cnt_1),
+ .A(FE_OFN6_o_cnt_1));
+ INVX1 FE_OFC1_o_cnt_3 (.Y(FE_OFN2_o_cnt_3),
+ .A(FE_OFN1_o_cnt_3));
+ DFFRHQX1 \rstn_sync_reg[1] (.Q(rstn_sync[1]),
+ .D(rstn_sync[0]),
+ .RN(i_rstn),
+ .CK(i_clk));
+ DFFRHQX1 \rstn_sync_reg[0] (.Q(rstn_sync[0]),
+ .D(1'b1),
+ .RN(i_rstn),
+ .CK(i_clk));
+ DFFRHQX1 \cnt_reg[3] (.Q(FE_OFN0_o_cnt_3),
+ .D(n_9),
+ .RN(rstn_sync[1]),
+ .CK(i_clk));
+ SDFFRHQX1 \cnt_reg[2] (.Q(FE_OFN3_o_cnt_2),
+ .D(n_6),
+ .SE(FE_OFN3_o_cnt_2),
+ .SI(n_7),
+ .RN(rstn_sync[1]),
+ .CK(i_clk));
+ OAI31X1 g337__8780 (.Y(n_9),
+ .A0(FE_OFN0_o_cnt_3),
+ .A1(FE_OFN4_o_cnt_2),
+ .A2(n_7),
+ .B0(n_8));
+ SDFFRHQX1 \cnt_reg[1] (.Q(FE_OFN5_o_cnt_1),
+ .D(FE_OFN5_o_cnt_1),
+ .SE(n_1),
+ .SI(n_4),
+ .RN(rstn_sync[1]),
+ .CK(i_clk));
+ AOI22X1 g339__4296 (.Y(n_8),
+ .A0(FE_OFN2_o_cnt_3),
+ .A1(n_5),
+ .B0(FE_OFN5_o_cnt_1),
+ .B1(n_2));
+ DFFRHQX1 \cnt_reg[0] (.Q(FE_OFN8_o_cnt_0),
+ .D(n_3),
+ .RN(rstn_sync[1]),
+ .CK(i_clk));
+ OAI21X1 g342__3772 (.Y(n_5),
+ .A0(FE_OFN7_o_cnt_1),
+ .A1(FE_OFN4_o_cnt_2),
+ .B0(n_1));
+ NAND2XL g343__1474 (.Y(n_7),
+ .A(FE_OFN5_o_cnt_1),
+ .B(n_1));
+ NOR2X1 g344__4547 (.Y(n_4),
+ .A(FE_OFN5_o_cnt_1),
+ .B(n_2));
+ AOI2BB1X1 g345__9682 (.Y(n_3),
+ .A0N(i_en),
+ .A1N(FE_OFN8_o_cnt_0),
+ .B0(n_1));
+ AND2X1 g346__2683 (.Y(n_2),
+ .A(FE_OFN4_o_cnt_2),
+ .B(FE_OFN0_o_cnt_3));
+ AND2X1 g347__1309 (.Y(n_1),
+ .A(i_en),
+ .B(FE_OFN8_o_cnt_0));
+endmodule
+
diff --git a/compteur/implementation/pnr/netlist/compteur.place.sdf b/compteur/implementation/pnr/netlist/compteur.place.sdf
new file mode 100644
index 0000000000000000000000000000000000000000..e01e751c1e3622b31edad4e1fb54882f11c7a743
--- /dev/null
+++ b/compteur/implementation/pnr/netlist/compteur.place.sdf
@@ -0,0 +1,287 @@
+(DELAYFILE
+ (SDFVERSION "2.1")
+ (DESIGN "compteur")
+ (DATE "Wed Oct 2 14:38:24 2019")
+ (VENDOR "Cadence Design Systems, Inc.")
+ (PROGRAM "Innovus")
+ (VERSION "v18.10-p002_1 ((64bit) 05/29/2018 19:19 (Linux 2.6.18-194.el5))")
+ (DIVIDER /)
+ (VOLTAGE 0.900000::0.900000)
+ (PROCESS "1.000000::1.000000")
+ (TEMPERATURE 125.000000::125.000000)
+ (TIMESCALE 1.0 ns)
+
+ (CELL
+ (CELLTYPE "compteur")
+ (INSTANCE)
+ (DELAY
+ (ABSOLUTE
+ (INTERCONNECT cnt_reg\[3\]/Q g337__8780/A0 (0.012::0.012) (0.012::0.012))
+ (INTERCONNECT cnt_reg\[3\]/Q g339__4296/A0 (0.012::0.012) (0.012::0.012))
+ (INTERCONNECT cnt_reg\[3\]/Q g346__2683/B (0.012::0.012) (0.012::0.012))
+ (INTERCONNECT cnt_reg\[2\]/Q cnt_reg\[2\]/SE (0.008::0.008) (0.008::0.008))
+ (INTERCONNECT cnt_reg\[2\]/Q g348/A (0.013::0.013) (0.013::0.013))
+ (INTERCONNECT cnt_reg\[1\]/Q cnt_reg\[1\]/D (0.008::0.008) (0.008::0.008))
+ (INTERCONNECT cnt_reg\[1\]/Q g339__4296/B0 (0.014::0.014) (0.014::0.014))
+ (INTERCONNECT cnt_reg\[1\]/Q g342__3772/A0 (0.019::0.019) (0.019::0.019))
+ (INTERCONNECT cnt_reg\[1\]/Q g343__1474/A (0.020::0.020) (0.020::0.020))
+ (INTERCONNECT cnt_reg\[1\]/Q g344__4547/A (0.012::0.012) (0.012::0.012))
+ (INTERCONNECT cnt_reg\[0\]/Q g345__9682/A1N (0.003::0.003) (0.003::0.003))
+ (INTERCONNECT cnt_reg\[0\]/Q g347__1309/B (0.003::0.003) (0.003::0.003))
+ (INTERCONNECT rstn_sync_reg\[1\]/Q cnt_reg\[3\]/RN (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT rstn_sync_reg\[1\]/Q cnt_reg\[2\]/RN (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT rstn_sync_reg\[1\]/Q cnt_reg\[1\]/RN (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT rstn_sync_reg\[1\]/Q cnt_reg\[0\]/RN (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT rstn_sync_reg\[0\]/Q rstn_sync_reg\[1\]/D (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g348/Y g337__8780/A1 (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g348/Y g342__3772/A1 (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g348/Y g346__2683/A (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g347__1309/Y cnt_reg\[1\]/SE (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g347__1309/Y g342__3772/B0 (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g347__1309/Y g343__1474/B (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g347__1309/Y g345__9682/B0 (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g346__2683/Y g339__4296/B1 (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g346__2683/Y g344__4547/B (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g345__9682/Y cnt_reg\[0\]/D (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g344__4547/Y cnt_reg\[1\]/SI (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g342__3772/Y g339__4296/A1 (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g341/Y cnt_reg\[2\]/D (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g343__1474/Y cnt_reg\[2\]/SI (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g343__1474/Y g337__8780/A2 (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g343__1474/Y g341/A (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g339__4296/Y g337__8780/B0 (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g337__8780/Y cnt_reg\[3\]/D (0.000::0.000) (0.000::0.000))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "DFFRHQX1")
+ (INSTANCE rstn_sync_reg\[1\])
+ (DELAY
+ (ABSOLUTE
+ (IOPATH RN Q () (0.072::0.072))
+ (IOPATH CK Q (0.231::0.231) (0.202::0.202))
+ )
+ )
+ (TIMINGCHECK
+ (WIDTH (negedge RN) (::0.135))
+ (SETUPHOLD (posedge D) (posedge CK) (::0.119) (::-0.073))
+ (SETUPHOLD (negedge D) (posedge CK) (::0.059) (::0.013))
+ (WIDTH (posedge CK) (::0.091))
+ (WIDTH (negedge CK) (::0.106))
+ )
+ )
+
+ (CELL
+ (CELLTYPE "DFFRHQX1")
+ (INSTANCE rstn_sync_reg\[0\])
+ (DELAY
+ (ABSOLUTE
+ (IOPATH RN Q () (0.076::0.076))
+ (IOPATH CK Q (0.235::0.235) (0.207::0.207))
+ )
+ )
+ (TIMINGCHECK
+ (WIDTH (negedge RN) (::0.135))
+ (SETUPHOLD (posedge D) (posedge CK) (::0.108) (::-0.062))
+ (SETUPHOLD (negedge D) (posedge CK) (::0.049) (::0.021))
+ (WIDTH (posedge CK) (::0.091))
+ (WIDTH (negedge CK) (::0.106))
+ )
+ )
+
+ (CELL
+ (CELLTYPE "DFFRHQX1")
+ (INSTANCE cnt_reg\[3\])
+ (DELAY
+ (ABSOLUTE
+ (IOPATH RN Q () (6.799::6.799))
+ (IOPATH CK Q (5.961::5.961) (6.939::6.939))
+ )
+ )
+ (TIMINGCHECK
+ (WIDTH (negedge RN) (::0.081))
+ (SETUPHOLD (posedge D) (posedge CK) (::0.294) (::-0.239))
+ (SETUPHOLD (negedge D) (posedge CK) (::0.342) (::-0.229))
+ (WIDTH (posedge CK) (::0.091))
+ (WIDTH (negedge CK) (::0.106))
+ )
+ )
+
+ (CELL
+ (CELLTYPE "SDFFRHQX1")
+ (INSTANCE cnt_reg\[2\])
+ (DELAY
+ (ABSOLUTE
+ (IOPATH RN Q () (6.802::6.802))
+ (IOPATH CK Q (5.963::5.963) (6.943::6.943))
+ )
+ )
+ (TIMINGCHECK
+ (WIDTH (negedge RN) (::0.081))
+ (SETUPHOLD (posedge SI) (posedge CK) (::1.302) (::-1.210))
+ (SETUPHOLD (negedge SI) (posedge CK) (::0.513) (::-0.394))
+ (SETUPHOLD (posedge SE) (posedge CK) (::5.252) (::-4.979))
+ (SETUPHOLD (negedge SE) (posedge CK) (::5.530) (::-4.803))
+ (SETUPHOLD (posedge D) (posedge CK) (::0.275) (::-0.211))
+ (SETUPHOLD (negedge D) (posedge CK) (::0.321) (::-0.217))
+ (WIDTH (posedge CK) (::0.091))
+ (WIDTH (negedge CK) (::0.101))
+ )
+ )
+
+ (CELL
+ (CELLTYPE "OAI31X1")
+ (INSTANCE g337__8780)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A0 Y (6.056::6.056) (6.026::6.026))
+ (IOPATH A1 Y (0.891::0.891) (1.156::1.156))
+ (IOPATH A2 Y (0.488::0.488) (1.291::1.291))
+ (IOPATH B0 Y (0.459::0.459) (0.808::0.808))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "SDFFRHQX1")
+ (INSTANCE cnt_reg\[1\])
+ (DELAY
+ (ABSOLUTE
+ (IOPATH RN Q () (6.810::6.810))
+ (IOPATH CK Q (5.968::5.968) (6.950::6.950))
+ )
+ )
+ (TIMINGCHECK
+ (WIDTH (negedge RN) (::0.081))
+ (SETUPHOLD (posedge SI) (posedge CK) (::0.611) (::-0.538))
+ (SETUPHOLD (negedge SI) (posedge CK) (::0.998) (::-0.844))
+ (SETUPHOLD (posedge SE) (posedge CK) (::0.232) (::-0.114))
+ (SETUPHOLD (negedge SE) (posedge CK) (::0.264) (::-0.072))
+ (SETUPHOLD (posedge D) (posedge CK) (::5.521) (::-5.314))
+ (SETUPHOLD (negedge D) (posedge CK) (::5.984) (::-5.503))
+ (WIDTH (posedge CK) (::0.091))
+ (WIDTH (negedge CK) (::0.101))
+ )
+ )
+
+ (CELL
+ (CELLTYPE "AOI22X1")
+ (INSTANCE g339__4296)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A0 Y (6.667::6.667) (5.967::5.967))
+ (IOPATH A1 Y (0.449::0.449) (0.527::0.527))
+ (IOPATH B0 Y (6.858::6.858) (5.943::5.943))
+ (IOPATH B1 Y (0.083::0.083) (0.089::0.089))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "DFFRHQX1")
+ (INSTANCE cnt_reg\[0\])
+ (DELAY
+ (ABSOLUTE
+ (IOPATH RN Q () (6.805::6.805))
+ (IOPATH CK Q (5.967::5.967) (6.945::6.945))
+ )
+ )
+ (TIMINGCHECK
+ (WIDTH (negedge RN) (::0.081))
+ (SETUPHOLD (posedge D) (posedge CK) (::0.138) (::-0.090))
+ (SETUPHOLD (negedge D) (posedge CK) (::0.086) (::-0.011))
+ (WIDTH (posedge CK) (::0.091))
+ (WIDTH (negedge CK) (::0.106))
+ )
+ )
+
+ (CELL
+ (CELLTYPE "INVX1")
+ (INSTANCE g341)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (0.480::0.480) (1.296::1.296))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "OAI21X1")
+ (INSTANCE g342__3772)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A0 Y (6.466::6.466) (5.966::5.966))
+ (IOPATH A1 Y (0.927::0.927) (1.126::1.126))
+ (IOPATH B0 Y (0.100::0.100) (0.136::0.136))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "NAND2X1")
+ (INSTANCE g343__1474)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (7.171::7.171) (5.938::5.938))
+ (IOPATH B Y (0.113::0.113) (0.151::0.151))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "NOR2X1")
+ (INSTANCE g344__4547)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (6.430::6.430) (6.288::6.288))
+ (IOPATH B Y (0.070::0.070) (0.063::0.063))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "AOI2BB1X1")
+ (INSTANCE g345__9682)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A0N Y (0.095::0.095) (0.116::0.116))
+ (IOPATH A1N Y (5.031::5.031) (5.421::5.421))
+ (IOPATH B0 Y (0.118::0.118) (0.104::0.104))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "AND2X1")
+ (INSTANCE g346__2683)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (0.998::0.998) (0.797::0.797))
+ (IOPATH B Y (5.288::5.288) (5.821::5.821))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "CLKAND2X3")
+ (INSTANCE g347__1309)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (0.105::0.105) (0.097::0.097))
+ (IOPATH B Y (4.588::4.588) (6.051::6.051))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "INVX3")
+ (INSTANCE g348)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (6.000::6.000) (5.210::5.210))
+ )
+ )
+ )
+)
diff --git a/compteur/implementation/pnr/netlist/compteur.place.v b/compteur/implementation/pnr/netlist/compteur.place.v
new file mode 100644
index 0000000000000000000000000000000000000000..a098964cc4f36ebca347b9731875e9c2a0ab3378
--- /dev/null
+++ b/compteur/implementation/pnr/netlist/compteur.place.v
@@ -0,0 +1,99 @@
+/*
+###############################################################
+# Generated by: Cadence Innovus 18.10-p002_1
+# OS: Linux x86_64(Host ID pcys41)
+# Generated on: Wed Oct 2 14:38:24 2019
+# Design: compteur
+# Command: saveNetlist /export/tmp/fiorentino/Projects/tutoriel_numerique/compteur/implementation/pnr/netlist/compteur.place.v
+###############################################################
+*/
+// Generated by Cadence Genus(TM) Synthesis Solution 18.10-p003_1
+// Generated on: Oct 2 2019 14:33:08 EDT (Oct 2 2019 18:33:08 UTC)
+// Verification Directory fv/compteur
+module compteur (
+ i_clk,
+ i_rstn,
+ i_en,
+ o_cnt);
+ input i_clk;
+ input i_rstn;
+ input i_en;
+ output [3:0] o_cnt;
+
+ // Internal wires
+ wire [1:0] rstn_sync;
+ wire n_0;
+ wire n_1;
+ wire n_2;
+ wire n_3;
+ wire n_4;
+ wire n_5;
+ wire n_6;
+ wire n_7;
+ wire n_8;
+ wire n_9;
+
+ DFFRHQX1 \rstn_sync_reg[1] (.Q(rstn_sync[1]),
+ .D(rstn_sync[0]),
+ .RN(i_rstn),
+ .CK(i_clk));
+ DFFRHQX1 \rstn_sync_reg[0] (.Q(rstn_sync[0]),
+ .D(1'b1),
+ .RN(i_rstn),
+ .CK(i_clk));
+ DFFRHQX1 \cnt_reg[3] (.Q(o_cnt[3]),
+ .D(n_9),
+ .RN(rstn_sync[1]),
+ .CK(i_clk));
+ SDFFRHQX1 \cnt_reg[2] (.Q(o_cnt[2]),
+ .D(n_6),
+ .SE(o_cnt[2]),
+ .SI(n_7),
+ .RN(rstn_sync[1]),
+ .CK(i_clk));
+ OAI31X1 g337__8780 (.Y(n_9),
+ .A0(o_cnt[3]),
+ .A1(n_0),
+ .A2(n_7),
+ .B0(n_8));
+ SDFFRHQX1 \cnt_reg[1] (.Q(o_cnt[1]),
+ .D(o_cnt[1]),
+ .SE(n_1),
+ .SI(n_4),
+ .RN(rstn_sync[1]),
+ .CK(i_clk));
+ AOI22X1 g339__4296 (.Y(n_8),
+ .A0(o_cnt[3]),
+ .A1(n_5),
+ .B0(o_cnt[1]),
+ .B1(n_2));
+ DFFRHQX1 \cnt_reg[0] (.Q(o_cnt[0]),
+ .D(n_3),
+ .RN(rstn_sync[1]),
+ .CK(i_clk));
+ INVX1 g341 (.Y(n_6),
+ .A(n_7));
+ OAI21X1 g342__3772 (.Y(n_5),
+ .A0(o_cnt[1]),
+ .A1(n_0),
+ .B0(n_1));
+ NAND2X1 g343__1474 (.Y(n_7),
+ .A(o_cnt[1]),
+ .B(n_1));
+ NOR2X1 g344__4547 (.Y(n_4),
+ .A(o_cnt[1]),
+ .B(n_2));
+ AOI2BB1X1 g345__9682 (.Y(n_3),
+ .A0N(i_en),
+ .A1N(o_cnt[0]),
+ .B0(n_1));
+ AND2X1 g346__2683 (.Y(n_2),
+ .A(n_0),
+ .B(o_cnt[3]));
+ CLKAND2X3 g347__1309 (.Y(n_1),
+ .A(i_en),
+ .B(o_cnt[0]));
+ INVX3 g348 (.Y(n_0),
+ .A(o_cnt[2]));
+endmodule
+
diff --git a/compteur/implementation/pnr/netlist/compteur.pnr.phy.v b/compteur/implementation/pnr/netlist/compteur.pnr.phy.v
deleted file mode 100644
index ac7533186f58814a56870b202f32ae3440eb89a0..0000000000000000000000000000000000000000
--- a/compteur/implementation/pnr/netlist/compteur.pnr.phy.v
+++ /dev/null
@@ -1,565 +0,0 @@
-/*
-###############################################################
-# Generated by: Cadence Innovus 17.11-s080_1
-# OS: Linux x86_64(Host ID pcys41)
-# Generated on: Tue Sep 10 10:50:11 2019
-# Design: compteur
-# Command: saveNetlist -phys /export/tmp/fiorentino/Projects/grm/tutoriel_numerique/compteur/implementation/pnr/netlist/compteur.pnr.phy.v
-###############################################################
-*/
-module BUFX20 (
- Y,
- A,
- VSS,
- VDD);
- output Y;
- input A;
- inout VSS;
- inout VDD;
-endmodule
-
-module INVX1 (
- Y,
- A,
- VSS,
- VDD);
- output Y;
- input A;
- inout VSS;
- inout VDD;
-endmodule
-
-module CLKINVX20 (
- Y,
- A,
- VSS,
- VDD);
- output Y;
- input A;
- inout VSS;
- inout VDD;
-endmodule
-
-module DFFRHQX1 (
- Q,
- D,
- RN,
- CK,
- VSS,
- VDD);
- output Q;
- input D;
- input RN;
- input CK;
- inout VSS;
- inout VDD;
-endmodule
-
-module OAI31X1 (
- Y,
- A0,
- A1,
- A2,
- B0,
- VSS,
- VDD);
- output Y;
- input A0;
- input A1;
- input A2;
- input B0;
- inout VSS;
- inout VDD;
-endmodule
-
-module XNOR2X1 (
- Y,
- A,
- B,
- VSS,
- VDD);
- output Y;
- input A;
- input B;
- inout VSS;
- inout VDD;
-endmodule
-
-module SDFFRHQX1 (
- Q,
- D,
- SE,
- SI,
- RN,
- CK,
- VSS,
- VDD);
- output Q;
- input D;
- input SE;
- input SI;
- input RN;
- input CK;
- inout VSS;
- inout VDD;
-endmodule
-
-module AOI22X1 (
- Y,
- A0,
- A1,
- B0,
- B1,
- VSS,
- VDD);
- output Y;
- input A0;
- input A1;
- input B0;
- input B1;
- inout VSS;
- inout VDD;
-endmodule
-
-module NAND2X1 (
- Y,
- A,
- B,
- VSS,
- VDD);
- output Y;
- input A;
- input B;
- inout VSS;
- inout VDD;
-endmodule
-
-module OAI21X1 (
- Y,
- A0,
- A1,
- B0,
- VSS,
- VDD);
- output Y;
- input A0;
- input A1;
- input B0;
- inout VSS;
- inout VDD;
-endmodule
-
-module NOR2X1 (
- Y,
- A,
- B,
- VSS,
- VDD);
- output Y;
- input A;
- input B;
- inout VSS;
- inout VDD;
-endmodule
-
-module ADDHX1 (
- CO,
- S,
- A,
- B,
- VSS,
- VDD);
- output CO;
- output S;
- input A;
- input B;
- inout VSS;
- inout VDD;
-endmodule
-
-module AND2X1 (
- Y,
- A,
- B,
- VSS,
- VDD);
- output Y;
- input A;
- input B;
- inout VSS;
- inout VDD;
-endmodule
-
-// Generated by Cadence Genus(TM) Synthesis Solution 17.10-p007_1
-// Generated on: Sep 10 2019 10:42:42 EDT (Sep 10 2019 14:42:42 UTC)
-// Verification Directory fv/compteur
-module compteur (
- i_clk,
- i_rstn,
- i_en,
- o_cnt,
- VDD,
- VSS);
- input i_clk;
- input i_rstn;
- input i_en;
- output [3:0] o_cnt;
- inout VDD;
- inout VSS;
-
- // Internal wires
- wire FE_OFN19_o_cnt_0;
- wire FE_OFN17_o_cnt_3;
- wire FE_OFN16_o_cnt_0;
- wire FE_OFN15_o_cnt_0;
- wire FE_OFN14_o_cnt_1;
- wire FE_OFN13_o_cnt_1;
- wire FE_OFN12_o_cnt_2;
- wire FE_OFN11_o_cnt_2;
- wire FE_OFN10_o_cnt_3;
- wire FE_OFN9_o_cnt_3;
- wire FE_OFN8_o_cnt_0;
- wire FE_OFN7_o_cnt_0;
- wire FE_OFN6_o_cnt_1;
- wire FE_OFN5_o_cnt_1;
- wire FE_OFN4_o_cnt_2;
- wire FE_OFN3_o_cnt_2;
- wire FE_OFN1_o_cnt_3;
- wire FE_OFN0_o_cnt_3;
- wire [1:0] rstn_sync;
- wire [3:0] cnt;
- wire n_8;
- wire n_9;
- wire n_11;
- wire n_12;
- wire n_13;
- wire n_16;
- wire n_17;
- wire n_18;
- wire n_19;
-
- // Module instantiations
- BUFX20 FE_OFC22_o_cnt_3 (
- .Y(o_cnt[3]),
- .A(FE_OFN17_o_cnt_3),
- .VSS(VSS),
- .VDD(VDD));
- BUFX20 FE_OFC20_o_cnt_0 (
- .Y(o_cnt[0]),
- .A(FE_OFN19_o_cnt_0),
- .VSS(VSS),
- .VDD(VDD));
- INVX1 FE_OFC16_o_cnt_0 (
- .Y(FE_OFN19_o_cnt_0),
- .A(FE_OFN16_o_cnt_0),
- .VSS(VSS),
- .VDD(VDD));
- INVX1 FE_OFC15_o_cnt_0 (
- .Y(FE_OFN16_o_cnt_0),
- .A(FE_OFN15_o_cnt_0),
- .VSS(VSS),
- .VDD(VDD));
- CLKINVX20 FE_OFC14_o_cnt_1 (
- .Y(o_cnt[1]),
- .A(FE_OFN14_o_cnt_1),
- .VSS(VSS),
- .VDD(VDD));
- INVX1 FE_OFC13_o_cnt_1 (
- .Y(FE_OFN14_o_cnt_1),
- .A(FE_OFN13_o_cnt_1),
- .VSS(VSS),
- .VDD(VDD));
- CLKINVX20 FE_OFC12_o_cnt_2 (
- .Y(o_cnt[2]),
- .A(FE_OFN12_o_cnt_2),
- .VSS(VSS),
- .VDD(VDD));
- INVX1 FE_OFC11_o_cnt_2 (
- .Y(FE_OFN12_o_cnt_2),
- .A(FE_OFN11_o_cnt_2),
- .VSS(VSS),
- .VDD(VDD));
- INVX1 FE_OFC10_o_cnt_3 (
- .Y(FE_OFN17_o_cnt_3),
- .A(FE_OFN10_o_cnt_3),
- .VSS(VSS),
- .VDD(VDD));
- INVX1 FE_OFC9_o_cnt_3 (
- .Y(FE_OFN10_o_cnt_3),
- .A(FE_OFN9_o_cnt_3),
- .VSS(VSS),
- .VDD(VDD));
- INVX1 FE_OFC8_o_cnt_0 (
- .Y(FE_OFN15_o_cnt_0),
- .A(FE_OFN8_o_cnt_0),
- .VSS(VSS),
- .VDD(VDD));
- INVX1 FE_OFC7_o_cnt_0 (
- .Y(FE_OFN8_o_cnt_0),
- .A(FE_OFN7_o_cnt_0),
- .VSS(VSS),
- .VDD(VDD));
- INVX1 FE_OFC6_o_cnt_1 (
- .Y(FE_OFN13_o_cnt_1),
- .A(FE_OFN6_o_cnt_1),
- .VSS(VSS),
- .VDD(VDD));
- INVX1 FE_OFC5_o_cnt_1 (
- .Y(FE_OFN6_o_cnt_1),
- .A(FE_OFN5_o_cnt_1),
- .VSS(VSS),
- .VDD(VDD));
- INVX1 FE_OFC4_o_cnt_2 (
- .Y(FE_OFN11_o_cnt_2),
- .A(FE_OFN4_o_cnt_2),
- .VSS(VSS),
- .VDD(VDD));
- INVX1 FE_OFC3_o_cnt_2 (
- .Y(FE_OFN4_o_cnt_2),
- .A(FE_OFN3_o_cnt_2),
- .VSS(VSS),
- .VDD(VDD));
- INVX1 FE_OFC2_o_cnt_3 (
- .Y(FE_OFN9_o_cnt_3),
- .A(FE_OFN1_o_cnt_3),
- .VSS(VSS),
- .VDD(VDD));
- INVX1 FE_OFC0_o_cnt_3 (
- .Y(FE_OFN1_o_cnt_3),
- .A(FE_OFN0_o_cnt_3),
- .VSS(VSS),
- .VDD(VDD));
- DFFRHQX1 \cnt_reg[3] (
- .Q(FE_OFN0_o_cnt_3),
- .D(n_19),
- .RN(rstn_sync[1]),
- .CK(i_clk),
- .VSS(VSS),
- .VDD(VDD));
- DFFRHQX1 \cnt_reg[2] (
- .Q(FE_OFN3_o_cnt_2),
- .D(n_18),
- .RN(rstn_sync[1]),
- .CK(i_clk),
- .VSS(VSS),
- .VDD(VDD));
- OAI31X1 g333__7837 (
- .Y(n_19),
- .A0(FE_OFN0_o_cnt_3),
- .A1(FE_OFN4_o_cnt_2),
- .A2(n_17),
- .B0(n_16),
- .VSS(VSS),
- .VDD(VDD));
- XNOR2X1 g336__7557 (
- .Y(n_18),
- .A(n_17),
- .B(FE_OFN3_o_cnt_2),
- .VSS(VSS),
- .VDD(VDD));
- SDFFRHQX1 \cnt_reg[1] (
- .Q(FE_OFN5_o_cnt_1),
- .D(FE_OFN5_o_cnt_1),
- .SE(n_13),
- .SI(n_11),
- .RN(rstn_sync[1]),
- .CK(i_clk),
- .VSS(VSS),
- .VDD(VDD));
- AOI22X1 g335__7654 (
- .Y(n_16),
- .A0(FE_OFN9_o_cnt_3),
- .A1(n_12),
- .B0(FE_OFN5_o_cnt_1),
- .B1(n_9),
- .VSS(VSS),
- .VDD(VDD));
- NAND2X1 g339__8867 (
- .Y(n_17),
- .A(FE_OFN5_o_cnt_1),
- .B(n_13),
- .VSS(VSS),
- .VDD(VDD));
- DFFRHQX1 \cnt_reg[0] (
- .Q(FE_OFN7_o_cnt_0),
- .D(n_8),
- .RN(rstn_sync[1]),
- .CK(i_clk),
- .VSS(VSS),
- .VDD(VDD));
- OAI21X1 g338__1377 (
- .Y(n_12),
- .A0(FE_OFN5_o_cnt_1),
- .A1(FE_OFN4_o_cnt_2),
- .B0(n_13),
- .VSS(VSS),
- .VDD(VDD));
- NOR2X1 g342__3717 (
- .Y(n_11),
- .A(FE_OFN5_o_cnt_1),
- .B(n_9),
- .VSS(VSS),
- .VDD(VDD));
- ADDHX1 g340__4599 (
- .CO(n_13),
- .S(n_8),
- .A(FE_OFN7_o_cnt_0),
- .B(i_en),
- .VSS(VSS),
- .VDD(VDD));
- AND2X1 g344__3779 (
- .Y(n_9),
- .A(FE_OFN4_o_cnt_2),
- .B(o_cnt[3]),
- .VSS(VSS),
- .VDD(VDD));
- DFFRHQX1 \rstn_sync_reg[1] (
- .Q(rstn_sync[1]),
- .D(rstn_sync[0]),
- .RN(i_rstn),
- .CK(i_clk),
- .VSS(VSS),
- .VDD(VDD));
- DFFRHQX1 \rstn_sync_reg[0] (
- .Q(rstn_sync[0]),
- .D(VDD),
- .RN(i_rstn),
- .CK(i_clk),
- .VSS(VSS),
- .VDD(VDD));
-
- // Fillers and physical instances.
- FILL1 FILLER_impl0_44 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL8 FILLER_impl0_43 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL1 FILLER_impl0_42 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL8 FILLER_impl0_41 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL1 FILLER_impl0_40 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL2 FILLER_impl0_39 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL4 FILLER_impl0_38 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL1 FILLER_impl0_37 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL2 FILLER_impl0_36 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL1 FILLER_impl0_35 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL2 FILLER_impl0_34 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL2 FILLER_impl0_33 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL4 FILLER_impl0_32 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL1 FILLER_impl0_31 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL2 FILLER_impl0_30 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL4 FILLER_impl0_29 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL1 FILLER_impl0_28 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL2 FILLER_impl0_27 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL1 FILLER_impl0_26 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL4 FILLER_impl0_25 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL8 FILLER_impl0_24 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL1 FILLER_impl0_23 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL2 FILLER_impl0_22 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL4 FILLER_impl0_21 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL8 FILLER_impl0_20 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL1 FILLER_impl0_19 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL4 FILLER_impl0_18 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL1 FILLER_impl0_17 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL2 FILLER_impl0_16 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL16 FILLER_impl0_15 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL1 FILLER_impl0_14 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL2 FILLER_impl0_13 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL1 FILLER_impl0_12 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL2 FILLER_impl0_11 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL8 FILLER_impl0_10 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL16 FILLER_impl0_9 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL2 FILLER_impl0_8 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL4 FILLER_impl0_7 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL1 FILLER_impl0_6 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL2 FILLER_impl0_5 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL1 FILLER_impl0_4 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL2 FILLER_impl0_3 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL16 FILLER_impl0_2 (
- .VDD(VDD),
- .VSS(VSS) );
- FILL2 FILLER_impl0_1 (
- .VDD(VDD),
- .VSS(VSS) );
-endmodule
-
diff --git a/compteur/implementation/pnr/netlist/compteur.pnr.sdf b/compteur/implementation/pnr/netlist/compteur.pnr.sdf
deleted file mode 100644
index 6bdf8d9844ef6cbbf3b76bc69ecb4c04442a7e63..0000000000000000000000000000000000000000
--- a/compteur/implementation/pnr/netlist/compteur.pnr.sdf
+++ /dev/null
@@ -1,477 +0,0 @@
-(DELAYFILE
- (SDFVERSION "3.0")
- (DESIGN "compteur")
- (DATE "Tue Sep 10 10:50:11 2019")
- (VENDOR "Cadence Design Systems, Inc.")
- (PROGRAM "Innovus")
- (VERSION "v17.11-s080_1 ((64bit) 08/04/2017 11:13 (Linux 2.6.18-194.el5))")
- (DIVIDER /)
- (VOLTAGE 1.100000::1.100000)
- (PROCESS "1.000000::1.000000")
- (TEMPERATURE 0.000000::0.000000)
- (TIMESCALE 1.0 ns)
-
- (CELL
- (CELLTYPE "compteur")
- (INSTANCE)
- (DELAY
- (ABSOLUTE
- (INTERCONNECT FE_OFC16_o_cnt_0/Y FE_OFC20_o_cnt_0/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC10_o_cnt_3/Y FE_OFC22_o_cnt_3/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC15_o_cnt_0/Y FE_OFC16_o_cnt_0/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC8_o_cnt_0/Y FE_OFC15_o_cnt_0/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC13_o_cnt_1/Y FE_OFC14_o_cnt_1/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC6_o_cnt_1/Y FE_OFC13_o_cnt_1/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC11_o_cnt_2/Y FE_OFC12_o_cnt_2/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC4_o_cnt_2/Y FE_OFC11_o_cnt_2/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC9_o_cnt_3/Y FE_OFC10_o_cnt_3/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC2_o_cnt_3/Y FE_OFC9_o_cnt_3/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC2_o_cnt_3/Y g335__7654/A0 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC7_o_cnt_0/Y FE_OFC8_o_cnt_0/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[0\]/Q FE_OFC7_o_cnt_0/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[0\]/Q g340__4599/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC5_o_cnt_1/Y FE_OFC6_o_cnt_1/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[1\]/Q FE_OFC5_o_cnt_1/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[1\]/Q cnt_reg\[1\]/D (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[1\]/Q g335__7654/B0 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[1\]/Q g339__8867/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[1\]/Q g338__1377/A0 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[1\]/Q g342__3717/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC3_o_cnt_2/Y FE_OFC4_o_cnt_2/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC3_o_cnt_2/Y g333__7837/A1 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC3_o_cnt_2/Y g338__1377/A1 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC3_o_cnt_2/Y g344__3779/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[2\]/Q FE_OFC3_o_cnt_2/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[2\]/Q g336__7557/B (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC0_o_cnt_3/Y FE_OFC2_o_cnt_3/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[3\]/Q FE_OFC0_o_cnt_3/A (0.000::0.000) (0.000::0.000))
- (INTERCONNECT cnt_reg\[3\]/Q g333__7837/A0 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT i_clk cnt_reg\[3\]/CK (0.000::0.000) (0.000::0.000))
- (INTERCONNECT i_clk cnt_reg\[2\]/CK (0.000::0.000) (0.000::0.000))
- (INTERCONNECT i_clk cnt_reg\[1\]/CK (0.000::0.000) (0.000::0.000))
- (INTERCONNECT i_clk cnt_reg\[0\]/CK (0.000::0.000) (0.000::0.000))
- (INTERCONNECT i_clk rstn_sync_reg\[1\]/CK (0.000::0.000) (0.000::0.000))
- (INTERCONNECT i_clk rstn_sync_reg\[0\]/CK (0.000::0.000) (0.000::0.000))
- (INTERCONNECT i_rstn rstn_sync_reg\[1\]/RN (0.000::0.000) (0.000::0.000))
- (INTERCONNECT i_rstn rstn_sync_reg\[0\]/RN (0.000::0.000) (0.000::0.000))
- (INTERCONNECT i_en g340__4599/B (0.000::0.000) (0.000::0.000))
- (INTERCONNECT FE_OFC22_o_cnt_3/Y g344__3779/B (0.000::0.007) (0.000::0.007))
- (INTERCONNECT rstn_sync_reg\[1\]/Q cnt_reg\[3\]/RN (0.000::0.000) (0.000::0.000))
- (INTERCONNECT rstn_sync_reg\[1\]/Q cnt_reg\[2\]/RN (0.000::0.000) (0.000::0.000))
- (INTERCONNECT rstn_sync_reg\[1\]/Q cnt_reg\[1\]/RN (0.000::0.000) (0.000::0.000))
- (INTERCONNECT rstn_sync_reg\[1\]/Q cnt_reg\[0\]/RN (0.000::0.000) (0.000::0.000))
- (INTERCONNECT rstn_sync_reg\[0\]/Q rstn_sync_reg\[1\]/D (0.000::0.000) (0.000::0.000))
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- (INTERCONNECT g338__1377/Y g335__7654/A1 (0.000::0.000) (0.000::0.000))
- (INTERCONNECT g340__4599/CO cnt_reg\[1\]/SE (0.000::0.000) (0.000::0.000))
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- )
- )
- )
-
- (CELL
- (CELLTYPE "BUFX20")
- (INSTANCE FE_OFC22_o_cnt_3)
- (DELAY
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- (CELL
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- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.008::0.008) (0.008::0.008))
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- (DELAY
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- )
- )
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- (CELL
- (CELLTYPE "INVX1")
- (INSTANCE FE_OFC13_o_cnt_1)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.019::0.041) (0.020::0.037))
- )
- )
- )
-
- (CELL
- (CELLTYPE "CLKINVX20")
- (INSTANCE FE_OFC12_o_cnt_2)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.014::0.226) (0.011::0.244))
- )
- )
- )
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- (CELL
- (CELLTYPE "INVX1")
- (INSTANCE FE_OFC11_o_cnt_2)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.019::0.041) (0.020::0.036))
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- (CELL
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- (INSTANCE FE_OFC10_o_cnt_3)
- (DELAY
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- (IOPATH A Y (0.015::0.016) (0.014::0.015))
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- (CELL
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- (INSTANCE FE_OFC9_o_cnt_3)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.010::0.010) (0.010::0.010))
- )
- )
- )
-
- (CELL
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- (INSTANCE FE_OFC8_o_cnt_0)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.009::0.009) (0.008::0.008))
- )
- )
- )
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- (CELL
- (CELLTYPE "INVX1")
- (INSTANCE FE_OFC7_o_cnt_0)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.010::0.010) (0.010::0.010))
- )
- )
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-
- (CELL
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- (INSTANCE FE_OFC6_o_cnt_1)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.009::0.009) (0.009::0.009))
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- )
- )
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- (CELL
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- (INSTANCE FE_OFC5_o_cnt_1)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.014::0.014) (0.015::0.015))
- )
- )
- )
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- (CELL
- (CELLTYPE "INVX1")
- (INSTANCE FE_OFC4_o_cnt_2)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.011::0.011) (0.012::0.012))
- )
- )
- )
-
- (CELL
- (CELLTYPE "INVX1")
- (INSTANCE FE_OFC3_o_cnt_2)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.015::0.016) (0.015::0.016))
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- )
- )
-
- (CELL
- (CELLTYPE "INVX1")
- (INSTANCE FE_OFC2_o_cnt_3)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.011::0.011) (0.010::0.011))
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- )
- )
-
- (CELL
- (CELLTYPE "INVX1")
- (INSTANCE FE_OFC0_o_cnt_3)
- (DELAY
- (ABSOLUTE
- (IOPATH A Y (0.009::0.009) (0.009::0.009))
- )
- )
- )
-
- (CELL
- (CELLTYPE "DFFRHQX1")
- (INSTANCE cnt_reg\[3\])
- (DELAY
- (ABSOLUTE
- (IOPATH RN Q () (0.028::0.028))
- (IOPATH (posedge CK) Q (0.059::0.060) (0.055::0.055))
- )
- )
- (TIMINGCHECK
- (WIDTH (negedge RN) (0.074::0.074))
- (RECREM (posedge RN) (posedge CK) (-0.013::-0.013) (0.033::0.033))
- (SETUPHOLD (posedge D) (posedge CK) (0.025::0.025) (-0.016::-0.016))
- (SETUPHOLD (negedge D) (posedge CK) (0.013::0.013) (0.001::0.001))
- (WIDTH (posedge CK) (0.034::0.034))
- (WIDTH (negedge CK) (0.039::0.039))
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- )
-
- (CELL
- (CELLTYPE "DFFRHQX1")
- (INSTANCE cnt_reg\[2\])
- (DELAY
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- )
- (TIMINGCHECK
- (WIDTH (negedge RN) (0.074::0.074))
- (RECREM (posedge RN) (posedge CK) (-0.013::-0.013) (0.033::0.033))
- (SETUPHOLD (posedge D) (posedge CK) (0.021::0.021) (-0.014::-0.014))
- (SETUPHOLD (negedge D) (posedge CK) (0.010::0.010) (0.002::0.002))
- (WIDTH (posedge CK) (0.034::0.034))
- (WIDTH (negedge CK) (0.039::0.039))
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- (INSTANCE g333__7837)
- (DELAY
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- (IOPATH A2 Y (0.026::0.027) (0.017::0.019))
- (IOPATH B0 Y (0.012::0.015) (0.024::0.026))
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- (IOPATH (posedge A) Y (0.033::0.034) (0.044::0.045))
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- (IOPATH (posedge B) Y (0.025::0.026) (0.031::0.031))
- (IOPATH (negedge B) Y (0.035::0.035) (0.030::0.031))
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- )
-
- (CELL
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- (INSTANCE cnt_reg\[1\])
- (DELAY
- (ABSOLUTE
- (IOPATH RN Q () (0.036::0.037))
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- (TIMINGCHECK
- (WIDTH (negedge RN) (0.074::0.074))
- (SETUPHOLD (posedge SI) (posedge CK) (0.037::0.037) (-0.029::-0.029))
- (SETUPHOLD (negedge SI) (posedge CK) (0.029::0.029) (-0.014::-0.014))
- (SETUPHOLD (posedge SE) (posedge CK) (0.034::0.034) (-0.018::-0.018))
- (SETUPHOLD (negedge SE) (posedge CK) (0.041::0.041) (-0.009::-0.009))
- (RECREM (posedge RN) (posedge CK) (-0.013::-0.013) (0.033::0.033))
- (SETUPHOLD (posedge D) (posedge CK) (0.041::0.041) (-0.033::-0.033))
- (SETUPHOLD (negedge D) (posedge CK) (0.031::0.031) (-0.017::-0.017))
- (WIDTH (posedge CK) (0.034::0.034))
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- (IOPATH B1 Y (0.018::0.019) (0.014::0.016))
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- (CELL
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- (INSTANCE g339__8867)
- (DELAY
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-
- (CELL
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- (DELAY
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- (TIMINGCHECK
- (WIDTH (negedge RN) (0.074::0.074))
- (RECREM (posedge RN) (posedge CK) (-0.013::-0.013) (0.033::0.033))
- (SETUPHOLD (posedge D) (posedge CK) (0.021::0.021) (-0.014::-0.014))
- (SETUPHOLD (negedge D) (posedge CK) (0.010::0.010) (0.002::0.002))
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- (WIDTH (negedge CK) (0.039::0.039))
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- (DELAY
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- (IOPATH A0 Y (0.025::0.025) (0.026::0.027))
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- (IOPATH B0 Y (0.012::0.013) (0.022::0.022))
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- (IOPATH (posedge B) S (0.027::0.028) (0.036::0.037))
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- (CELL
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- (IOPATH RN Q () (0.033::0.034))
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- (TIMINGCHECK
- (WIDTH (negedge RN) (0.032::0.032))
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- )
- )
-)
diff --git a/compteur/implementation/pnr/netlist/compteur.pnr.v b/compteur/implementation/pnr/netlist/compteur.pnr.v
deleted file mode 100644
index 201ff5247e16827dbff67e994ed9e8a4ebf9f5b7..0000000000000000000000000000000000000000
--- a/compteur/implementation/pnr/netlist/compteur.pnr.v
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
-###############################################################
-# Generated by: Cadence Innovus 17.11-s080_1
-# OS: Linux x86_64(Host ID pcys41)
-# Generated on: Tue Sep 10 10:50:11 2019
-# Design: compteur
-# Command: saveNetlist /export/tmp/fiorentino/Projects/grm/tutoriel_numerique/compteur/implementation/pnr/netlist/compteur.pnr.v
-###############################################################
-*/
-// Generated by Cadence Genus(TM) Synthesis Solution 17.10-p007_1
-// Generated on: Sep 10 2019 10:42:42 EDT (Sep 10 2019 14:42:42 UTC)
-// Verification Directory fv/compteur
-module compteur (
- i_clk,
- i_rstn,
- i_en,
- o_cnt);
- input i_clk;
- input i_rstn;
- input i_en;
- output [3:0] o_cnt;
-
- // Internal wires
- wire FE_OFN19_o_cnt_0;
- wire FE_OFN17_o_cnt_3;
- wire FE_OFN16_o_cnt_0;
- wire FE_OFN15_o_cnt_0;
- wire FE_OFN14_o_cnt_1;
- wire FE_OFN13_o_cnt_1;
- wire FE_OFN12_o_cnt_2;
- wire FE_OFN11_o_cnt_2;
- wire FE_OFN10_o_cnt_3;
- wire FE_OFN9_o_cnt_3;
- wire FE_OFN8_o_cnt_0;
- wire FE_OFN7_o_cnt_0;
- wire FE_OFN6_o_cnt_1;
- wire FE_OFN5_o_cnt_1;
- wire FE_OFN4_o_cnt_2;
- wire FE_OFN3_o_cnt_2;
- wire FE_OFN1_o_cnt_3;
- wire FE_OFN0_o_cnt_3;
- wire [1:0] rstn_sync;
- wire [3:0] cnt;
- wire n_8;
- wire n_9;
- wire n_11;
- wire n_12;
- wire n_13;
- wire n_16;
- wire n_17;
- wire n_18;
- wire n_19;
-
- BUFX20 FE_OFC22_o_cnt_3 (.Y(o_cnt[3]),
- .A(FE_OFN17_o_cnt_3));
- BUFX20 FE_OFC20_o_cnt_0 (.Y(o_cnt[0]),
- .A(FE_OFN19_o_cnt_0));
- INVX1 FE_OFC16_o_cnt_0 (.Y(FE_OFN19_o_cnt_0),
- .A(FE_OFN16_o_cnt_0));
- INVX1 FE_OFC15_o_cnt_0 (.Y(FE_OFN16_o_cnt_0),
- .A(FE_OFN15_o_cnt_0));
- CLKINVX20 FE_OFC14_o_cnt_1 (.Y(o_cnt[1]),
- .A(FE_OFN14_o_cnt_1));
- INVX1 FE_OFC13_o_cnt_1 (.Y(FE_OFN14_o_cnt_1),
- .A(FE_OFN13_o_cnt_1));
- CLKINVX20 FE_OFC12_o_cnt_2 (.Y(o_cnt[2]),
- .A(FE_OFN12_o_cnt_2));
- INVX1 FE_OFC11_o_cnt_2 (.Y(FE_OFN12_o_cnt_2),
- .A(FE_OFN11_o_cnt_2));
- INVX1 FE_OFC10_o_cnt_3 (.Y(FE_OFN17_o_cnt_3),
- .A(FE_OFN10_o_cnt_3));
- INVX1 FE_OFC9_o_cnt_3 (.Y(FE_OFN10_o_cnt_3),
- .A(FE_OFN9_o_cnt_3));
- INVX1 FE_OFC8_o_cnt_0 (.Y(FE_OFN15_o_cnt_0),
- .A(FE_OFN8_o_cnt_0));
- INVX1 FE_OFC7_o_cnt_0 (.Y(FE_OFN8_o_cnt_0),
- .A(FE_OFN7_o_cnt_0));
- INVX1 FE_OFC6_o_cnt_1 (.Y(FE_OFN13_o_cnt_1),
- .A(FE_OFN6_o_cnt_1));
- INVX1 FE_OFC5_o_cnt_1 (.Y(FE_OFN6_o_cnt_1),
- .A(FE_OFN5_o_cnt_1));
- INVX1 FE_OFC4_o_cnt_2 (.Y(FE_OFN11_o_cnt_2),
- .A(FE_OFN4_o_cnt_2));
- INVX1 FE_OFC3_o_cnt_2 (.Y(FE_OFN4_o_cnt_2),
- .A(FE_OFN3_o_cnt_2));
- INVX1 FE_OFC2_o_cnt_3 (.Y(FE_OFN9_o_cnt_3),
- .A(FE_OFN1_o_cnt_3));
- INVX1 FE_OFC0_o_cnt_3 (.Y(FE_OFN1_o_cnt_3),
- .A(FE_OFN0_o_cnt_3));
- DFFRHQX1 \cnt_reg[3] (.Q(FE_OFN0_o_cnt_3),
- .D(n_19),
- .RN(rstn_sync[1]),
- .CK(i_clk));
- DFFRHQX1 \cnt_reg[2] (.Q(FE_OFN3_o_cnt_2),
- .D(n_18),
- .RN(rstn_sync[1]),
- .CK(i_clk));
- OAI31X1 g333__7837 (.Y(n_19),
- .A0(FE_OFN0_o_cnt_3),
- .A1(FE_OFN4_o_cnt_2),
- .A2(n_17),
- .B0(n_16));
- XNOR2X1 g336__7557 (.Y(n_18),
- .A(n_17),
- .B(FE_OFN3_o_cnt_2));
- SDFFRHQX1 \cnt_reg[1] (.Q(FE_OFN5_o_cnt_1),
- .D(FE_OFN5_o_cnt_1),
- .SE(n_13),
- .SI(n_11),
- .RN(rstn_sync[1]),
- .CK(i_clk));
- AOI22X1 g335__7654 (.Y(n_16),
- .A0(FE_OFN9_o_cnt_3),
- .A1(n_12),
- .B0(FE_OFN5_o_cnt_1),
- .B1(n_9));
- NAND2X1 g339__8867 (.Y(n_17),
- .A(FE_OFN5_o_cnt_1),
- .B(n_13));
- DFFRHQX1 \cnt_reg[0] (.Q(FE_OFN7_o_cnt_0),
- .D(n_8),
- .RN(rstn_sync[1]),
- .CK(i_clk));
- OAI21X1 g338__1377 (.Y(n_12),
- .A0(FE_OFN5_o_cnt_1),
- .A1(FE_OFN4_o_cnt_2),
- .B0(n_13));
- NOR2X1 g342__3717 (.Y(n_11),
- .A(FE_OFN5_o_cnt_1),
- .B(n_9));
- ADDHX1 g340__4599 (.CO(n_13),
- .S(n_8),
- .A(FE_OFN7_o_cnt_0),
- .B(i_en));
- AND2X1 g344__3779 (.Y(n_9),
- .A(FE_OFN4_o_cnt_2),
- .B(o_cnt[3]));
- DFFRHQX1 \rstn_sync_reg[1] (.Q(rstn_sync[1]),
- .D(rstn_sync[0]),
- .RN(i_rstn),
- .CK(i_clk));
- DFFRHQX1 \rstn_sync_reg[0] (.Q(rstn_sync[0]),
- .D(1'b1),
- .RN(i_rstn),
- .CK(i_clk));
-endmodule
-
diff --git a/compteur/implementation/pnr/netlist/compteur.route.sdf b/compteur/implementation/pnr/netlist/compteur.route.sdf
new file mode 100644
index 0000000000000000000000000000000000000000..520704f948cbd3e6cd8d4b431e386c3292bd5a73
--- /dev/null
+++ b/compteur/implementation/pnr/netlist/compteur.route.sdf
@@ -0,0 +1,375 @@
+(DELAYFILE
+ (SDFVERSION "2.1")
+ (DESIGN "compteur")
+ (DATE "Wed Oct 2 14:39:39 2019")
+ (VENDOR "Cadence Design Systems, Inc.")
+ (PROGRAM "Innovus")
+ (VERSION "v18.10-p002_1 ((64bit) 05/29/2018 19:19 (Linux 2.6.18-194.el5))")
+ (DIVIDER /)
+ (VOLTAGE 0.900000::0.900000)
+ (PROCESS "1.000000::1.000000")
+ (TEMPERATURE 125.000000::125.000000)
+ (TIMESCALE 1.0 ns)
+
+ (CELL
+ (CELLTYPE "compteur")
+ (INSTANCE)
+ (DELAY
+ (ABSOLUTE
+ (INTERCONNECT cnt_reg\[0\]/Q g345__9682/A1N (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT cnt_reg\[0\]/Q g347__1309/B (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT cnt_reg\[0\]/Q FE_OFC26_FE_OFN8_o_cnt_0/A (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT FE_OFC7_o_cnt_1/Y g342__3772/A0 (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT FE_OFC22_FE_OFN5_o_cnt_1/Y FE_OFC7_o_cnt_1/A (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT cnt_reg\[1\]/Q g339__4296/B0 (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT cnt_reg\[1\]/Q g344__4547/A (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT cnt_reg\[1\]/Q cnt_reg\[1\]/D (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT cnt_reg\[1\]/Q g343__1474/A (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT cnt_reg\[1\]/Q FE_OFC22_FE_OFN5_o_cnt_1/A (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT cnt_reg\[1\]/Q FE_OFC23_FE_OFN5_o_cnt_1/A (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT FE_OFC20_FE_OFN3_o_cnt_2/Y FE_OFC21_FE_OFN3_o_cnt_2/A (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT FE_OFC20_FE_OFN3_o_cnt_2/Y g337__8780/A1 (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT FE_OFC20_FE_OFN3_o_cnt_2/Y g346__2683/A (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT FE_OFC20_FE_OFN3_o_cnt_2/Y g342__3772/A1 (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT cnt_reg\[2\]/Q cnt_reg\[2\]/SE (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT cnt_reg\[2\]/Q FE_OFC20_FE_OFN3_o_cnt_2/A (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT FE_OFC1_o_cnt_3/Y g339__4296/A0 (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT FE_OFC24_FE_OFN0_o_cnt_3/Y FE_OFC1_o_cnt_3/A (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT cnt_reg\[3\]/Q g337__8780/A0 (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT cnt_reg\[3\]/Q g346__2683/B (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT cnt_reg\[3\]/Q FE_OFC24_FE_OFN0_o_cnt_3/A (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT cnt_reg\[3\]/Q FE_OFC25_FE_OFN0_o_cnt_3/A (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT rstn_sync_reg\[1\]/Q cnt_reg\[3\]/RN (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT rstn_sync_reg\[1\]/Q cnt_reg\[2\]/RN (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT rstn_sync_reg\[1\]/Q cnt_reg\[1\]/RN (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT rstn_sync_reg\[1\]/Q cnt_reg\[0\]/RN (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT rstn_sync_reg\[0\]/Q rstn_sync_reg\[1\]/D (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g347__1309/Y cnt_reg\[1\]/SE (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g347__1309/Y g342__3772/B0 (0.000::0.000) (0.000::0.000))
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+ (INTERCONNECT g346__2683/Y g344__4547/B (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g345__9682/Y cnt_reg\[0\]/D (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g344__4547/Y cnt_reg\[1\]/SI (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g342__3772/Y g339__4296/A1 (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT FE_OFC27_n_7/Y cnt_reg\[2\]/D (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g343__1474/Y g337__8780/A2 (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g343__1474/Y cnt_reg\[2\]/SI (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g343__1474/Y FE_OFC27_n_7/A (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g339__4296/Y g337__8780/B0 (0.000::0.000) (0.000::0.000))
+ (INTERCONNECT g337__8780/Y cnt_reg\[3\]/D (0.000::0.000) (0.000::0.000))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "INVX1")
+ (INSTANCE FE_OFC27_n_7)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (0.127::0.127) (0.077::0.077))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "CLKBUFX20")
+ (INSTANCE FE_OFC26_FE_OFN8_o_cnt_0)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (0.408::0.408) (0.480::0.480))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "CLKBUFX20")
+ (INSTANCE FE_OFC25_FE_OFN0_o_cnt_3)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (0.415::0.415) (0.487::0.487))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "INVX1")
+ (INSTANCE FE_OFC24_FE_OFN0_o_cnt_3)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (0.071::0.071) (0.073::0.073))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "CLKBUFX20")
+ (INSTANCE FE_OFC23_FE_OFN5_o_cnt_1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (0.424::0.424) (0.498::0.498))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "INVX1")
+ (INSTANCE FE_OFC22_FE_OFN5_o_cnt_1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (0.092::0.092) (0.093::0.093))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "CLKINVX20")
+ (INSTANCE FE_OFC21_FE_OFN3_o_cnt_2)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (0.380::0.380) (0.459::0.459))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "INVX2")
+ (INSTANCE FE_OFC20_FE_OFN3_o_cnt_2)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (0.095::0.095) (0.102::0.102))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "INVX1")
+ (INSTANCE FE_OFC7_o_cnt_1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (0.042::0.042) (0.044::0.044))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "INVX1")
+ (INSTANCE FE_OFC1_o_cnt_3)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (0.036::0.036) (0.038::0.038))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "DFFRHQX1")
+ (INSTANCE rstn_sync_reg\[1\])
+ (DELAY
+ (ABSOLUTE
+ (IOPATH RN Q () (0.072::0.072))
+ (IOPATH CK Q (0.242::0.242) (0.213::0.213))
+ )
+ )
+ (TIMINGCHECK
+ (WIDTH (negedge RN) (0.135::0.135))
+ (SETUPHOLD (posedge D) (posedge CK) (0.113::0.113) (-0.067::-0.067))
+ (SETUPHOLD (negedge D) (posedge CK) (0.046::0.046) (0.026::0.026))
+ (WIDTH (posedge CK) (0.152::0.152))
+ (WIDTH (negedge CK) (0.165::0.165))
+ )
+ )
+
+ (CELL
+ (CELLTYPE "DFFRHQX1")
+ (INSTANCE rstn_sync_reg\[0\])
+ (DELAY
+ (ABSOLUTE
+ (IOPATH RN Q () (0.079::0.079))
+ (IOPATH CK Q (0.249::0.249) (0.221::0.221))
+ )
+ )
+ (TIMINGCHECK
+ (WIDTH (negedge RN) (0.135::0.135))
+ (SETUPHOLD (posedge D) (posedge CK) (0.100::0.100) (-0.054::-0.054))
+ (SETUPHOLD (negedge D) (posedge CK) (0.034::0.034) (0.036::0.036))
+ (WIDTH (posedge CK) (0.152::0.152))
+ (WIDTH (negedge CK) (0.165::0.165))
+ )
+ )
+
+ (CELL
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+ (INSTANCE cnt_reg\[3\])
+ (DELAY
+ (ABSOLUTE
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+ (IOPATH CK Q (0.286::0.286) (0.261::0.261))
+ )
+ )
+ (TIMINGCHECK
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+ (SETUPHOLD (posedge D) (posedge CK) (0.157::0.157) (-0.073::-0.073))
+ (SETUPHOLD (negedge D) (posedge CK) (0.078::0.078) (0.009::0.009))
+ (WIDTH (posedge CK) (0.152::0.152))
+ (WIDTH (negedge CK) (0.165::0.165))
+ )
+ )
+
+ (CELL
+ (CELLTYPE "SDFFRHQX1")
+ (INSTANCE cnt_reg\[2\])
+ (DELAY
+ (ABSOLUTE
+ (IOPATH RN Q () (0.088::0.088))
+ (IOPATH CK Q (0.266::0.266) (0.239::0.239))
+ )
+ )
+ (TIMINGCHECK
+ (WIDTH (negedge RN) (0.081::0.081))
+ (SETUPHOLD (posedge SI) (posedge CK) (0.233::0.233) (-0.164::-0.164))
+ (SETUPHOLD (negedge SI) (posedge CK) (0.208::0.208) (-0.110::-0.110))
+ (SETUPHOLD (posedge SE) (posedge CK) (0.187::0.187) (-0.066::-0.066))
+ (SETUPHOLD (negedge SE) (posedge CK) (0.218::0.218) (-0.026::-0.026))
+ (SETUPHOLD (posedge D) (posedge CK) (0.211::0.211) (-0.149::-0.149))
+ (SETUPHOLD (negedge D) (posedge CK) (0.130::0.130) (-0.038::-0.038))
+ (WIDTH (posedge CK) (0.152::0.152))
+ (WIDTH (negedge CK) (0.161::0.161))
+ )
+ )
+
+ (CELL
+ (CELLTYPE "OAI31X1")
+ (INSTANCE g337__8780)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A0 Y (0.159::0.159) (0.146::0.146))
+ (IOPATH A1 Y (0.165::0.165) (0.146::0.146))
+ (IOPATH A2 Y (0.177::0.177) (0.117::0.117))
+ (IOPATH B0 Y (0.080::0.080) (0.125::0.125))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "SDFFRHQX1")
+ (INSTANCE cnt_reg\[1\])
+ (DELAY
+ (ABSOLUTE
+ (IOPATH RN Q () (0.131::0.131))
+ (IOPATH CK Q (0.305::0.305) (0.281::0.281))
+ )
+ )
+ (TIMINGCHECK
+ (WIDTH (negedge RN) (0.081::0.081))
+ (SETUPHOLD (posedge SI) (posedge CK) (0.210::0.210) (-0.147::-0.147))
+ (SETUPHOLD (negedge SI) (posedge CK) (0.140::0.140) (-0.038::-0.038))
+ (SETUPHOLD (posedge SE) (posedge CK) (0.196::0.196) (-0.074::-0.074))
+ (SETUPHOLD (negedge SE) (posedge CK) (0.227::0.227) (-0.032::-0.032))
+ (SETUPHOLD (posedge D) (posedge CK) (0.249::0.249) (-0.184::-0.184))
+ (SETUPHOLD (negedge D) (posedge CK) (0.176::0.176) (-0.080::-0.080))
+ (WIDTH (posedge CK) (0.152::0.152))
+ (WIDTH (negedge CK) (0.161::0.161))
+ )
+ )
+
+ (CELL
+ (CELLTYPE "AOI22X1")
+ (INSTANCE g339__4296)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A0 Y (0.090::0.090) (0.105::0.105))
+ (IOPATH A1 Y (0.113::0.113) (0.127::0.127))
+ (IOPATH B0 Y (0.129::0.129) (0.126::0.126))
+ (IOPATH B1 Y (0.068::0.068) (0.069::0.069))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "DFFRHQX1")
+ (INSTANCE cnt_reg\[0\])
+ (DELAY
+ (ABSOLUTE
+ (IOPATH RN Q () (0.103::0.103))
+ (IOPATH CK Q (0.279::0.279) (0.253::0.253))
+ )
+ )
+ (TIMINGCHECK
+ (WIDTH (negedge RN) (0.081::0.081))
+ (SETUPHOLD (posedge D) (posedge CK) (0.128::0.128) (-0.079::-0.079))
+ (SETUPHOLD (negedge D) (posedge CK) (0.055::0.055) (0.023::0.023))
+ (WIDTH (posedge CK) (0.152::0.152))
+ (WIDTH (negedge CK) (0.165::0.165))
+ )
+ )
+
+ (CELL
+ (CELLTYPE "OAI21X1")
+ (INSTANCE g342__3772)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A0 Y (0.076::0.076) (0.091::0.091))
+ (IOPATH A1 Y (0.120::0.120) (0.125::0.125))
+ (IOPATH B0 Y (0.063::0.063) (0.105::0.105))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "NAND2XL")
+ (INSTANCE g343__1474)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (0.133::0.133) (0.205::0.205))
+ (IOPATH B Y (0.094::0.094) (0.164::0.164))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "NOR2X1")
+ (INSTANCE g344__4547)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (0.114::0.114) (0.102::0.102))
+ (IOPATH B Y (0.055::0.055) (0.042::0.042))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "AOI2BB1X1")
+ (INSTANCE g345__9682)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A0N Y (0.096::0.096) (0.117::0.117))
+ (IOPATH A1N Y (0.112::0.112) (0.131::0.131))
+ (IOPATH B0 Y (0.087::0.087) (0.071::0.071))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "AND2X1")
+ (INSTANCE g346__2683)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (0.172::0.172) (0.121::0.121))
+ (IOPATH B Y (0.172::0.172) (0.113::0.113))
+ )
+ )
+ )
+
+ (CELL
+ (CELLTYPE "AND2X1")
+ (INSTANCE g347__1309)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH A Y (0.149::0.149) (0.095::0.095))
+ (IOPATH B Y (0.184::0.184) (0.128::0.128))
+ )
+ )
+ )
+)
diff --git a/compteur/implementation/pnr/netlist/compteur.route.v b/compteur/implementation/pnr/netlist/compteur.route.v
new file mode 100644
index 0000000000000000000000000000000000000000..e385e114232672b8f3d6f338b9d2a36c2f3eb837
--- /dev/null
+++ b/compteur/implementation/pnr/netlist/compteur.route.v
@@ -0,0 +1,123 @@
+/*
+###############################################################
+# Generated by: Cadence Innovus 18.10-p002_1
+# OS: Linux x86_64(Host ID pcys41)
+# Generated on: Wed Oct 2 14:39:38 2019
+# Design: compteur
+# Command: saveNetlist /export/tmp/fiorentino/Projects/tutoriel_numerique/compteur/implementation/pnr/netlist/compteur.route.v
+###############################################################
+*/
+// Generated by Cadence Genus(TM) Synthesis Solution 18.10-p003_1
+// Generated on: Oct 2 2019 14:33:08 EDT (Oct 2 2019 18:33:08 UTC)
+// Verification Directory fv/compteur
+module compteur (
+ i_clk,
+ i_rstn,
+ i_en,
+ o_cnt);
+ input i_clk;
+ input i_rstn;
+ input i_en;
+ output [3:0] o_cnt;
+
+ // Internal wires
+ wire FE_OFN8_o_cnt_0;
+ wire FE_OFN7_o_cnt_1;
+ wire FE_OFN6_o_cnt_1;
+ wire FE_OFN5_o_cnt_1;
+ wire FE_OFN4_o_cnt_2;
+ wire FE_OFN3_o_cnt_2;
+ wire FE_OFN2_o_cnt_3;
+ wire FE_OFN1_o_cnt_3;
+ wire FE_OFN0_o_cnt_3;
+ wire [1:0] rstn_sync;
+ wire n_1;
+ wire n_2;
+ wire n_3;
+ wire n_4;
+ wire n_5;
+ wire n_6;
+ wire n_7;
+ wire n_8;
+ wire n_9;
+
+ INVX1 FE_OFC27_n_7 (.Y(n_6),
+ .A(n_7));
+ CLKBUFX20 FE_OFC26_FE_OFN8_o_cnt_0 (.Y(o_cnt[0]),
+ .A(FE_OFN8_o_cnt_0));
+ CLKBUFX20 FE_OFC25_FE_OFN0_o_cnt_3 (.Y(o_cnt[3]),
+ .A(FE_OFN0_o_cnt_3));
+ INVX1 FE_OFC24_FE_OFN0_o_cnt_3 (.Y(FE_OFN1_o_cnt_3),
+ .A(FE_OFN0_o_cnt_3));
+ CLKBUFX20 FE_OFC23_FE_OFN5_o_cnt_1 (.Y(o_cnt[1]),
+ .A(FE_OFN5_o_cnt_1));
+ INVX1 FE_OFC22_FE_OFN5_o_cnt_1 (.Y(FE_OFN6_o_cnt_1),
+ .A(FE_OFN5_o_cnt_1));
+ CLKINVX20 FE_OFC21_FE_OFN3_o_cnt_2 (.Y(o_cnt[2]),
+ .A(FE_OFN4_o_cnt_2));
+ INVX2 FE_OFC20_FE_OFN3_o_cnt_2 (.Y(FE_OFN4_o_cnt_2),
+ .A(FE_OFN3_o_cnt_2));
+ INVX1 FE_OFC7_o_cnt_1 (.Y(FE_OFN7_o_cnt_1),
+ .A(FE_OFN6_o_cnt_1));
+ INVX1 FE_OFC1_o_cnt_3 (.Y(FE_OFN2_o_cnt_3),
+ .A(FE_OFN1_o_cnt_3));
+ DFFRHQX1 \rstn_sync_reg[1] (.Q(rstn_sync[1]),
+ .D(rstn_sync[0]),
+ .RN(i_rstn),
+ .CK(i_clk));
+ DFFRHQX1 \rstn_sync_reg[0] (.Q(rstn_sync[0]),
+ .D(1'b1),
+ .RN(i_rstn),
+ .CK(i_clk));
+ DFFRHQX1 \cnt_reg[3] (.Q(FE_OFN0_o_cnt_3),
+ .D(n_9),
+ .RN(rstn_sync[1]),
+ .CK(i_clk));
+ SDFFRHQX1 \cnt_reg[2] (.Q(FE_OFN3_o_cnt_2),
+ .D(n_6),
+ .SE(FE_OFN3_o_cnt_2),
+ .SI(n_7),
+ .RN(rstn_sync[1]),
+ .CK(i_clk));
+ OAI31X1 g337__8780 (.Y(n_9),
+ .A0(FE_OFN0_o_cnt_3),
+ .A1(FE_OFN4_o_cnt_2),
+ .A2(n_7),
+ .B0(n_8));
+ SDFFRHQX1 \cnt_reg[1] (.Q(FE_OFN5_o_cnt_1),
+ .D(FE_OFN5_o_cnt_1),
+ .SE(n_1),
+ .SI(n_4),
+ .RN(rstn_sync[1]),
+ .CK(i_clk));
+ AOI22X1 g339__4296 (.Y(n_8),
+ .A0(FE_OFN2_o_cnt_3),
+ .A1(n_5),
+ .B0(FE_OFN5_o_cnt_1),
+ .B1(n_2));
+ DFFRHQX1 \cnt_reg[0] (.Q(FE_OFN8_o_cnt_0),
+ .D(n_3),
+ .RN(rstn_sync[1]),
+ .CK(i_clk));
+ OAI21X1 g342__3772 (.Y(n_5),
+ .A0(FE_OFN7_o_cnt_1),
+ .A1(FE_OFN4_o_cnt_2),
+ .B0(n_1));
+ NAND2XL g343__1474 (.Y(n_7),
+ .A(FE_OFN5_o_cnt_1),
+ .B(n_1));
+ NOR2X1 g344__4547 (.Y(n_4),
+ .A(FE_OFN5_o_cnt_1),
+ .B(n_2));
+ AOI2BB1X1 g345__9682 (.Y(n_3),
+ .A0N(i_en),
+ .A1N(FE_OFN8_o_cnt_0),
+ .B0(n_1));
+ AND2X1 g346__2683 (.Y(n_2),
+ .A(FE_OFN4_o_cnt_2),
+ .B(FE_OFN0_o_cnt_3));
+ AND2X1 g347__1309 (.Y(n_1),
+ .A(i_en),
+ .B(FE_OFN8_o_cnt_0));
+endmodule
+
diff --git a/compteur/implementation/pnr/reports/compteur.con.rpt b/compteur/implementation/pnr/reports/compteur.con.rpt
index 00e69d41f684dfa3f43fad16ee9759e9a68e3bab..89ce38ba275ba48cc8b55c8e04af3b7215da362a 100644
--- a/compteur/implementation/pnr/reports/compteur.con.rpt
+++ b/compteur/implementation/pnr/reports/compteur.con.rpt
@@ -1,16 +1,16 @@
###############################################################
-# Generated by: Cadence Innovus 17.11-s080_1
+# Generated by: Cadence Innovus 18.10-p002_1
# OS: Linux x86_64(Host ID pcys41)
-# Generated on: Tue Sep 10 10:50:10 2019
+# Generated on: Wed Oct 2 14:39:37 2019
# Design: compteur
-# Command: verifyConnectivity -type all -error 1000 -warning 50 -report /export/tmp/fiorentino/Projects/grm/tutoriel_numerique/compteur/implementation/pnr/reports/compteur.con.rpt
+# Command: verifyConnectivity -type all -error 1000 -warning 50 -report /export/tmp/fiorentino/Projects/tutoriel_numerique/compteur/implementation/pnr/reports/compteur.con.rpt
###############################################################
-Verify Connectivity Report is created on Tue Sep 10 10:50:10 2019
+Verify Connectivity Report is created on Wed Oct 2 14:39:37 2019
-Net VSS: dangling Wire at (15.900, 1.140) (15.900, 1.140) on layer: Metal1
-Net VSS: dangling Wire at (15.900, 11.400) (15.900, 11.400) on layer: Metal1
+Net VSS: dangling Wire at (16.300, 1.140) (16.300, 1.140) on layer: Metal1
+Net VSS: dangling Wire at (16.300, 11.400) (16.300, 11.400) on layer: Metal1
Begin Summary
2 Problem(s) (IMPVFC-94): The net has dangling wire(s).
diff --git a/compteur/implementation/pnr/reports/compteur.drc.rpt b/compteur/implementation/pnr/reports/compteur.drc.rpt
index 57e70cbef8f097d7ca905f574b1e71b78e25a794..6fad5b1b6d7e24389476236ad13c8bceebc22c8e 100644
--- a/compteur/implementation/pnr/reports/compteur.drc.rpt
+++ b/compteur/implementation/pnr/reports/compteur.drc.rpt
@@ -1,11 +1,11 @@
###############################################################
-# Generated by: Cadence Innovus 17.11-s080_1
+# Generated by: Cadence Innovus 18.10-p002_1
# OS: Linux x86_64(Host ID pcys41)
-# Generated on: Tue Sep 10 10:50:10 2019
+# Generated on: Wed Oct 2 14:39:37 2019
# Design: compteur
# Command: verify_drc
###############################################################
-#set_verify_drc_mode -report /export/tmp/fiorentino/Projects/grm/tutoriel_numerique/compteur/implementation/pnr/reports/compteur.drc.rpt
+#set_verify_drc_mode -report /export/tmp/fiorentino/Projects/tutoriel_numerique/compteur/implementation/pnr/reports/compteur.drc.rpt
No DRC violations were found
diff --git a/compteur/implementation/pnr/reports/compteur.dyn.rpt b/compteur/implementation/pnr/reports/compteur.dyn.rpt
index e5e5326751de1de0e8e0a25fbb12f2ad4db9535a..479a1361f73a18e7070fb8cab3004bae90036de9 100644
--- a/compteur/implementation/pnr/reports/compteur.dyn.rpt
+++ b/compteur/implementation/pnr/reports/compteur.dyn.rpt
@@ -2,26 +2,26 @@
* Voltus Power Analysis - Power Calculator - Version v16.16-s020_1 64-bit (05/03/2017 02:27:51)
* Copyright 2007, Cadence Design Systems, Inc.
*
-* Date & Time: 2019-Sep-10 11:33:16 (2019-Sep-10 15:33:16 GMT)
+* Date & Time: 2019-Oct-02 15:11:52 (2019-Oct-02 19:11:52 GMT)
*
*----------------------------------------------------------------------------------------
*
* Design: compteur
*
* Liberty Libraries used:
-* /CMC/kits/GPDK45/gsclib045/gsclib045/timing/fast_vdd1v0_basicCells.lib
+* /CMC/kits/GPDK45/gsclib045/gsclib045/timing/slow_vdd1v0_basicCells.lib
*
* Power Domain used:
-* Rail: VDD Voltage: 1.1
+* Rail: VDD Voltage: 0.9
*
* DEF Files used:
-* /tmp/ssv_tmpdir_30932_IDtqud/eps_out_30932.def.gz
+* /tmp/ssv_tmpdir_24667_PxDrwd/eps_out_24667.def.gz
*
* Switching Activity File used:
-* /export/tmp/fiorentino/Projects/grm/tutoriel_numerique/compteur/simulation/pnr/compteur.pnr.vcd
-* Vcd Window used(Start Time, Stop Time): (0,39)
+* /export/tmp/fiorentino/Projects/tutoriel_numerique/compteur/simulation/pnr/compteur.vcd
+* Vcd Window used(Start Time, Stop Time): (0,54375)
* Vcd Scale Factor: 1
-* * Design annotation coverage: 36/36 = 100%
+* * Design annotation coverage: 27/27 = 100%
*
* Hierarchical Global Activity: N.A.
*
@@ -39,46 +39,46 @@
*
* Time Units = 1e-09 secs
*
-* report_power -output /export/tmp/fiorentino/Projects/grm/tutoriel_numerique/compteur/implementation/pnr/reports/power -format detailed -report_prefix compteur.dyn
+* report_power -output /export/tmp/fiorentino/Projects/tutoriel_numerique/compteur/implementation/pnr/reports/power -format detailed -report_prefix compteur.dyn
*
-----------------------------------------------------------------------------------------
Total Power
-----------------------------------------------------------------------------------------
-Total Internal Power: 0.05537990 6.7855%
-Total Switching Power: 0.76076285 93.2136%
-Total Leakage Power: 0.00000767 0.0009%
-Total Power: 0.81615044
+Total Internal Power: 0.02794941 12.0624%
+Total Switching Power: 0.20375353 87.9360%
+Total Leakage Power: 0.00000367 0.0016%
+Total Power: 0.23170661
-----------------------------------------------------------------------------------------
Group Internal Switching Leakage Total Percentage
Power Power Power Power (%)
-----------------------------------------------------------------------------------------
-Sequential 0.03352 0.001222 2.426e-06 0.03474 4.257
+Sequential 0.01723 0.001124 8.766e-07 0.01835 7.921
Macro 0 0 0 0 0
IO 0 0 0 0 0
-Combinational 0.02186 0.7595 5.246e-06 0.7814 95.74
+Combinational 0.01072 0.2026 2.793e-06 0.2134 92.08
Clock (Combinational) 0 0 0 0 0
Clock (Sequential) 0 0 0 0 0
-----------------------------------------------------------------------------------------
-Total 0.05538 0.7608 7.672e-06 0.8162 100
+Total 0.02795 0.2038 3.669e-06 0.2317 100
-----------------------------------------------------------------------------------------
Rail Voltage Internal Switching Leakage Total Percentage
Power Power Power Power (%)
-----------------------------------------------------------------------------------------
-VDD 1.1 0 0 0 0 0
+VDD 0.9 0 0 0 0 0
-----------------------------------------------------------------------------------------
* Power Distribution Summary:
-* Highest Average Power: FE_OFC20_o_cnt_0 (BUFX20): 0.4437
-* Highest Leakage Power: FE_OFC20_o_cnt_0 (BUFX20): 1.022e-06
-* Total Cap: 4.03721e-12 F
-* Total instances in design: 32
+* Highest Average Power: FE_OFC26_FE_OFN8_o_cnt_0 (CLKBUFX20): 0.1113
+* Highest Leakage Power: FE_OFC25_FE_OFN0_o_cnt_3 (CLKBUFX20): 6.246e-07
+* Total Cap: 2.03147e-12 F
+* Total instances in design: 24
* Total instances in design with no power: 0
* Total instances in design with no activity: 0
* Total Fillers and Decap: 0
diff --git a/compteur/implementation/pnr/reports/compteur.stat.rpt b/compteur/implementation/pnr/reports/compteur.stat.rpt
index 734c02f18d727e2050db693e37078a3eee395871..a3cee456d1314d433e0aa6941e1df75859d43a09 100644
--- a/compteur/implementation/pnr/reports/compteur.stat.rpt
+++ b/compteur/implementation/pnr/reports/compteur.stat.rpt
@@ -2,19 +2,19 @@
* Voltus IC Power Integrity Solution 16.16-s051_1 (64bit) 05/16/2017 12:06 (Linux 2.6.18-194.el5)
*
*
-* Date & Time: 2019-Sep-10 11:03:52 (2019-Sep-10 15:03:52 GMT)
+* Date & Time: 2019-Oct-02 15:09:34 (2019-Oct-02 19:09:34 GMT)
*
*----------------------------------------------------------------------------------------
*
* Design: compteur
*
* Liberty Libraries used:
-* av_fast: /CMC/kits/GPDK45/gsclib045/gsclib045/timing/fast_vdd1v0_basicCells.lib
+* slow_av: /CMC/kits/GPDK45/gsclib045/gsclib045/timing/slow_vdd1v0_basicCells.lib
*
* Power Domain used:
-* Rail: VDD Voltage: 1.1
+* Rail: VDD Voltage: 0.9
*
-* Power View : av_fast
+* Power View : slow_av
*
* User-Defined Activity : N.A.
*
@@ -36,46 +36,46 @@
*
* Time Units = 1e-09 secs
*
-* report_power -output /export/tmp/fiorentino/Projects/grm/tutoriel_numerique/compteur/implementation/pnr/reports/power -report_prefix compteur.stat -format detailed
+* report_power -output /export/tmp/fiorentino/Projects/tutoriel_numerique/compteur/implementation/pnr/reports/power -report_prefix compteur.stat -format detailed
*
-----------------------------------------------------------------------------------------
Total Power
-----------------------------------------------------------------------------------------
-Total Internal Power: 0.04981982 6.4300%
-Total Switching Power: 0.72497510 93.5690%
-Total Leakage Power: 0.00000781 0.0010%
-Total Power: 0.77480273
+Total Internal Power: 0.02651278 12.1526%
+Total Switching Power: 0.19164970 87.8458%
+Total Leakage Power: 0.00000367 0.0017%
+Total Power: 0.21816615
-----------------------------------------------------------------------------------------
Group Internal Switching Leakage Total Percentage
Power Power Power Power (%)
-----------------------------------------------------------------------------------------
-Sequential 0.03148 0.001147 2.442e-06 0.03263 4.212
+Sequential 0.01681 0.001026 9.016e-07 0.01783 8.174
Macro 0 0 0 0 0
IO 0 0 0 0 0
-Combinational 0.01834 0.7238 5.369e-06 0.7422 95.79
+Combinational 0.009707 0.1906 2.772e-06 0.2003 91.83
Clock (Combinational) 0 0 0 0 0
Clock (Sequential) 0 0 0 0 0
-----------------------------------------------------------------------------------------
-Total 0.04982 0.725 7.811e-06 0.7748 100
+Total 0.02651 0.1916 3.674e-06 0.2182 100
-----------------------------------------------------------------------------------------
Rail Voltage Internal Switching Leakage Total Percentage
Power Power Power Power (%)
-----------------------------------------------------------------------------------------
-VDD 1.1 0.04982 0.725 7.811e-06 0.7748 100
+VDD 0.9 0.02651 0.1916 3.674e-06 0.2182 100
-----------------------------------------------------------------------------------------
* Power Distribution Summary:
-* Highest Average Power: FE_OFC14_o_cnt_1 (CLKINVX20): 0.2095
-* Highest Leakage Power: FE_OFC20_o_cnt_0 (BUFX20): 1.034e-06
-* Total Cap: 4.04623e-12 F
-* Total instances in design: 32
+* Highest Average Power: FE_OFC23_FE_OFN5_o_cnt_1 (CLKBUFX20): 0.06309
+* Highest Leakage Power: FE_OFC23_FE_OFN5_o_cnt_1 (CLKBUFX20): 6.197e-07
+* Total Cap: 2.02968e-12 F
+* Total instances in design: 24
* Total instances in design with no power: 0
* Total instances in design with no activity: 0
* Total Fillers and Decap: 0
diff --git a/compteur/implementation/pnr/reports/compteur.timing.rpt b/compteur/implementation/pnr/reports/compteur.timing.rpt
index 8d9d669cfc242b35da80172062f1c972c1b737d3..d87d08ac6615eca67aa59cb0716fc7d9ce41a04c 100644
--- a/compteur/implementation/pnr/reports/compteur.timing.rpt
+++ b/compteur/implementation/pnr/reports/compteur.timing.rpt
@@ -1,35 +1,34 @@
###############################################################
-# Generated by: Cadence Innovus 17.11-s080_1
+# Generated by: Cadence Innovus 18.10-p002_1
# OS: Linux x86_64(Host ID pcys41)
-# Generated on: Tue Sep 10 10:50:10 2019
+# Generated on: Wed Oct 2 14:39:38 2019
# Design: compteur
# Command: report_timing > $::env(PNR_REP_DIR)/${DESIGN}.timing.rpt
###############################################################
Path 1: MET Late External Delay Assertion
-Endpoint: o_cnt[1] (v) checked with leading edge of 'clk'
-Beginpoint: cnt_reg[1]/Q (v) triggered by leading edge of 'clk'
+Endpoint: o_cnt[2] (v) checked with leading edge of 'clk'
+Beginpoint: cnt_reg[2]/Q (v) triggered by leading edge of 'clk'
Path Groups: {clk}
-Analysis View: av_fast
+Analysis View: slow_av
Other End Arrival Time 0.000
-- External Delay 0.300
-+ Phase Shift 1.000
+- External Delay 0.200
++ Phase Shift 1.250
++ CPPR Adjustment 0.000
- Uncertainty 0.100
-= Required Time 0.600
-- Arrival Time 0.380
-= Slack Time 0.220
+= Required Time 0.950
+- Arrival Time 0.796
+= Slack Time 0.154
Clock Rise Edge 0.000
- + Clock Network Latency (Prop) 0.000
- = Beginpoint Arrival Time 0.000
- +-------------------------------------------------------------------------+
- | Instance | Arc | Cell | Delay | Arrival | Required |
- | | | | | Time | Time |
- |------------------+-------------+-----------+-------+---------+----------|
- | cnt_reg[1] | CK ^ | | | 0.000 | 0.220 |
- | cnt_reg[1] | CK ^ -> Q v | SDFFRHQX1 | 0.064 | 0.064 | 0.284 |
- | FE_OFC5_o_cnt_1 | A v -> Y ^ | INVX1 | 0.014 | 0.078 | 0.298 |
- | FE_OFC6_o_cnt_1 | A ^ -> Y v | INVX1 | 0.009 | 0.087 | 0.307 |
- | FE_OFC13_o_cnt_1 | A v -> Y ^ | INVX1 | 0.041 | 0.128 | 0.348 |
- | FE_OFC14_o_cnt_1 | A ^ -> Y v | CLKINVX20 | 0.244 | 0.371 | 0.592 |
- | | o_cnt[1] v | | 0.008 | 0.380 | 0.600 |
- +-------------------------------------------------------------------------+
+ + Clock Network Latency (Prop) -0.000
+ = Beginpoint Arrival Time -0.000
+ +---------------------------------------------------------------------------------+
+ | Instance | Arc | Cell | Delay | Arrival | Required |
+ | | | | | Time | Time |
+ |--------------------------+-------------+-----------+-------+---------+----------|
+ | cnt_reg[2] | CK ^ | | | -0.000 | 0.154 |
+ | cnt_reg[2] | CK ^ -> Q v | SDFFRHQX1 | 0.239 | 0.239 | 0.393 |
+ | FE_OFC20_FE_OFN3_o_cnt_2 | A v -> Y ^ | INVX2 | 0.095 | 0.334 | 0.488 |
+ | FE_OFC21_FE_OFN3_o_cnt_2 | A ^ -> Y v | CLKINVX20 | 0.459 | 0.794 | 0.947 |
+ | | o_cnt[2] v | | 0.003 | 0.796 | 0.950 |
+ +---------------------------------------------------------------------------------+
diff --git a/compteur/implementation/pnr/timing/compteur_postCTS.cap.gz b/compteur/implementation/pnr/timing/compteur_postCTS.cap.gz
new file mode 100644
index 0000000000000000000000000000000000000000..7a726c05e5d1690774145dfbd834a87e262c49c8
Binary files /dev/null and b/compteur/implementation/pnr/timing/compteur_postCTS.cap.gz differ
diff --git a/compteur/implementation/pnr/timing/compteur_postCTS.fanout.gz b/compteur/implementation/pnr/timing/compteur_postCTS.fanout.gz
new file mode 100644
index 0000000000000000000000000000000000000000..f3a68d4aa53c861dd836fa443cfac4eb38c0f8f5
Binary files /dev/null and b/compteur/implementation/pnr/timing/compteur_postCTS.fanout.gz differ
diff --git a/compteur/implementation/pnr/timing/compteur_postCTS.length.gz b/compteur/implementation/pnr/timing/compteur_postCTS.length.gz
new file mode 100644
index 0000000000000000000000000000000000000000..dbe344debe7315db63bfa67171c5f28c74b9c9c6
Binary files /dev/null and b/compteur/implementation/pnr/timing/compteur_postCTS.length.gz differ
diff --git a/compteur/implementation/pnr/timing/compteur_postCTS.summary.gz b/compteur/implementation/pnr/timing/compteur_postCTS.summary.gz
new file mode 100644
index 0000000000000000000000000000000000000000..3884713d36dcaee408d23351096ec9f9bef7e3a0
Binary files /dev/null and b/compteur/implementation/pnr/timing/compteur_postCTS.summary.gz differ
diff --git a/compteur/implementation/pnr/timing/compteur_postCTS.tran.gz b/compteur/implementation/pnr/timing/compteur_postCTS.tran.gz
new file mode 100644
index 0000000000000000000000000000000000000000..66f329569658491feb35869aa6b0fc3a7d9ab268
Binary files /dev/null and b/compteur/implementation/pnr/timing/compteur_postCTS.tran.gz differ
diff --git a/compteur/implementation/pnr/timing/compteur_postCTS_all.tarpt.gz b/compteur/implementation/pnr/timing/compteur_postCTS_all.tarpt.gz
new file mode 100644
index 0000000000000000000000000000000000000000..8c85198bc227eb58536290b9a464fa24f455a34c
Binary files /dev/null and b/compteur/implementation/pnr/timing/compteur_postCTS_all.tarpt.gz differ
diff --git a/compteur/implementation/pnr/timing/compteur_postCTS_default.tarpt.gz b/compteur/implementation/pnr/timing/compteur_postCTS_default.tarpt.gz
new file mode 100644
index 0000000000000000000000000000000000000000..6da04943265bca4a38990a6a2a33434639220604
Binary files /dev/null and b/compteur/implementation/pnr/timing/compteur_postCTS_default.tarpt.gz differ
diff --git a/compteur/implementation/pnr/timing/compteur_postCTS_reg2reg.tarpt.gz b/compteur/implementation/pnr/timing/compteur_postCTS_reg2reg.tarpt.gz
new file mode 100644
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diff --git a/compteur/implementation/pnr/timing/compteur_prePlace.summary.gz b/compteur/implementation/pnr/timing/compteur_prePlace.summary.gz
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index 0000000000000000000000000000000000000000..31fcdfa15607925b65da52193709699bcb883deb
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diff --git a/compteur/implementation/pnr/timing/compteur_prePlace_reg2reg.tarpt.gz b/compteur/implementation/pnr/timing/compteur_prePlace_reg2reg.tarpt.gz
new file mode 100644
index 0000000000000000000000000000000000000000..01f9faba8efdf89b7486aa5aff77e4d36a557878
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diff --git a/compteur/implementation/syn/.gitignore b/compteur/implementation/syn/.gitignore
deleted file mode 100644
index d90dde6a2db294e859118caf08ee31603b8344f9..0000000000000000000000000000000000000000
--- a/compteur/implementation/syn/.gitignore
+++ /dev/null
@@ -1,4 +0,0 @@
-*~
-*.log
-*.cmd
-fv/
diff --git a/compteur/implementation/syn/netlist/compteur.elab.v b/compteur/implementation/syn/netlist/compteur.elab.v
new file mode 100644
index 0000000000000000000000000000000000000000..d8787fb506e8b1ca76801e2a355562bc3d0c4932
--- /dev/null
+++ b/compteur/implementation/syn/netlist/compteur.elab.v
@@ -0,0 +1,154 @@
+
+// Generated by Cadence Genus(TM) Synthesis Solution 18.10-p003_1
+// Generated on: Oct 2 2019 14:33:05 EDT (Oct 2 2019 18:33:05 UTC)
+
+// Verification Directory fv/compteur
+
+module add_unsigned(A, B, Z);
+ input [3:0] A;
+ input B;
+ output [3:0] Z;
+ wire [3:0] A;
+ wire B;
+ wire [3:0] Z;
+ wire n_11, n_18, n_21, n_28, n_30, n_34, n_35, n_37;
+ wire n_38;
+ xor g1 (Z[0], A[0], B);
+ nand g2 (n_11, A[0], B);
+ nand g13 (n_21, n_18, A[1]);
+ nand g20 (n_30, n_28, A[2]);
+ xnor g25 (Z[1], n_18, n_34);
+ xnor g27 (Z[2], n_28, n_35);
+ xnor g30 (Z[3], n_37, n_38);
+ not g35 (n_18, n_11);
+ not g36 (n_34, A[1]);
+ not g37 (n_35, A[2]);
+ not g38 (n_38, A[3]);
+ not g39 (n_28, n_21);
+ not g40 (n_37, n_30);
+endmodule
+
+module bmux(ctl, in_0, in_1, z);
+ input ctl;
+ input [1:0] in_0, in_1;
+ output [1:0] z;
+ wire ctl;
+ wire [1:0] in_0, in_1;
+ wire [1:0] z;
+ CDN_bmux2 g1(.sel0 (ctl), .data0 (in_0[1]), .data1 (in_1[1]), .z
+ (z[1]));
+ CDN_bmux2 g2(.sel0 (ctl), .data0 (in_0[0]), .data1 (in_1[0]), .z
+ (z[0]));
+endmodule
+
+module bmux_7(ctl, in_0, in_1, z);
+ input ctl;
+ input [3:0] in_0, in_1;
+ output [3:0] z;
+ wire ctl;
+ wire [3:0] in_0, in_1;
+ wire [3:0] z;
+ CDN_bmux2 g1(.sel0 (ctl), .data0 (in_0[3]), .data1 (in_1[3]), .z
+ (z[3]));
+ CDN_bmux2 g2(.sel0 (ctl), .data0 (in_0[2]), .data1 (in_1[2]), .z
+ (z[2]));
+ CDN_bmux2 g3(.sel0 (ctl), .data0 (in_0[1]), .data1 (in_1[1]), .z
+ (z[1]));
+ CDN_bmux2 g4(.sel0 (ctl), .data0 (in_0[0]), .data1 (in_1[0]), .z
+ (z[0]));
+endmodule
+
+module compteur(i_clk, i_rstn, i_en, o_cnt);
+ input i_clk, i_rstn, i_en;
+ output [3:0] o_cnt;
+ wire i_clk, i_rstn, i_en;
+ wire [3:0] o_cnt;
+ wire [3:0] plus_57_22;
+ wire [1:0] rstn_sync;
+ wire UNCONNECTED, UNCONNECTED0, UNCONNECTED1, UNCONNECTED2,
+ UNCONNECTED3, UNCONNECTED4, n_20, n_21;
+ wire n_23, n_24, n_25, n_26, n_27, n_43, n_44, n_46;
+ add_unsigned add_57_22(.A (o_cnt), .B (1'b1), .Z (plus_57_22));
+ bmux mux_rstn_sync_39_16(.ctl (n_20), .in_0 ({rstn_sync[0], 1'b1}),
+ .in_1 (2'b00), .z ({UNCONNECTED0, UNCONNECTED}));
+ bmux_7 mux_cnt_54_17(.ctl (n_23), .in_0 (plus_57_22), .in_1
+ (4'b0000), .z ({n_27, n_26, n_25, n_24}));
+ bmux_7 mux_cnt_50_14(.ctl (n_21), .in_0 ({n_27, n_26, n_25, n_24}),
+ .in_1 (4'b0000), .z ({UNCONNECTED4, UNCONNECTED3, UNCONNECTED2,
+ UNCONNECTED1}));
+ CDN_flop \rstn_sync_reg[0] (.clk (i_clk), .d (1'b0), .sena (1'b0),
+ .aclr (n_20), .apre (1'b0), .srl (1'b1), .srd (1'b1), .q
+ (rstn_sync[0]));
+ CDN_flop \rstn_sync_reg[1] (.clk (i_clk), .d (rstn_sync[0]), .sena
+ (1'b1), .aclr (n_20), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q
+ (rstn_sync[1]));
+ CDN_flop \cnt_reg[0] (.clk (i_clk), .d (n_24), .sena (i_en), .aclr
+ (n_21), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (o_cnt[0]));
+ CDN_flop \cnt_reg[1] (.clk (i_clk), .d (n_25), .sena (i_en), .aclr
+ (n_21), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (o_cnt[1]));
+ CDN_flop \cnt_reg[2] (.clk (i_clk), .d (n_26), .sena (i_en), .aclr
+ (n_21), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (o_cnt[2]));
+ CDN_flop \cnt_reg[3] (.clk (i_clk), .d (n_27), .sena (i_en), .aclr
+ (n_21), .apre (1'b0), .srl (1'b0), .srd (1'b0), .q (o_cnt[3]));
+ nand g18 (n_46, o_cnt[0], n_43, n_44, o_cnt[3]);
+ not g19 (n_23, n_46);
+ not g20 (n_20, i_rstn);
+ not g21 (n_21, rstn_sync[1]);
+ not g22 (n_43, o_cnt[1]);
+ not g23 (n_44, o_cnt[2]);
+endmodule
+
+`ifdef RC_CDN_GENERIC_GATE
+`else
+module CDN_flop(clk, d, sena, aclr, apre, srl, srd, q);
+ input clk, d, sena, aclr, apre, srl, srd;
+ output q;
+ wire clk, d, sena, aclr, apre, srl, srd;
+ wire q;
+ reg qi;
+ assign #1 q = qi;
+ always
+ @(posedge clk or posedge apre or posedge aclr)
+ if (aclr)
+ qi <= 0;
+ else if (apre)
+ qi <= 1;
+ else if (srl)
+ qi <= srd;
+ else begin
+ if (sena)
+ qi <= d;
+ end
+ initial
+ qi <= 1'b0;
+endmodule
+`endif
+`ifdef RC_CDN_GENERIC_GATE
+`else
+`ifdef ONE_HOT_MUX
+module CDN_bmux2(sel0, data0, data1, z);
+ input sel0, data0, data1;
+ output z;
+ wire sel0, data0, data1;
+ reg z;
+ always
+ @(sel0 or data0 or data1)
+ case ({sel0})
+ 1'b0: z = data0;
+ 1'b1: z = data1;
+ endcase
+endmodule
+`else
+module CDN_bmux2(sel0, data0, data1, z);
+ input sel0, data0, data1;
+ output z;
+ wire sel0, data0, data1;
+ wire z;
+ wire inv_sel0, w_0, w_1;
+ not i_0 (inv_sel0, sel0);
+ and a_0 (w_0, inv_sel0, data0);
+ and a_1 (w_1, sel0, data1);
+ or org (z, w_0, w_1);
+endmodule
+`endif // ONE_HOT_MUX
+`endif
diff --git a/compteur/implementation/syn/netlist/compteur.syn.sdf b/compteur/implementation/syn/netlist/compteur.syn.sdf
index a45e2c06dcaf8aedd0aaacce64d657319f2662db..ee77b43c81a491ce87b542f6f2de60bc3897de3d 100644
--- a/compteur/implementation/syn/netlist/compteur.syn.sdf
+++ b/compteur/implementation/syn/netlist/compteur.syn.sdf
@@ -1,76 +1,118 @@
(DELAYFILE
- (SDFVERSION "OVI 3.0")
+ (SDFVERSION "OVI 2.1")
(DESIGN "compteur")
- (DATE "Tue Sep 10 10:42:42 EDT 2019")
+ (DATE "Wed Oct 02 14:33:08 EDT 2019")
(VENDOR "Cadence, Inc.")
(PROGRAM "Genus(TM) Synthesis Solution")
- (VERSION "17.10-p007_1")
+ (VERSION "18.10-p003_1")
(DIVIDER .)
- (VOLTAGE ::1.1)
+ (VOLTAGE ::0.9)
(PROCESS "::1.0")
- (TEMPERATURE ::0.0)
+ (TEMPERATURE ::125.0)
(TIMESCALE 1ps)
(CELL
(CELLTYPE "DFFRHQX1")
- (INSTANCE cnt_reg\[3\])
+ (INSTANCE rstn_sync_reg\[1\])
(DELAY
(ABSOLUTE
(PORT RN (::0.0))
(PORT CK (::0.0))
(PORT D (::0.0))
- (IOPATH RN Q () (::45))
- (IOPATH CK Q (::81) (::75))
+ (IOPATH RN Q () (::71))
+ (IOPATH CK Q (::227) (::198))
)
)
(TIMINGCHECK
- (RECREM (posedge RN) (posedge CK) (::-20) (::27))
- (SETUPHOLD (negedge D) (posedge CK) (::18) (::-5))
- (SETUPHOLD (posedge D) (posedge CK) (::31) (::-24))
+ (HOLD (posedge RN) (posedge CK) (::99))
+ (RECOVERY (posedge RN) (posedge CK) (::0.0))
+ (HOLD (negedge D) (posedge CK) (::0.0))
+ (HOLD (posedge D) (posedge CK) (::0.0))
+ (SETUP (negedge D) (posedge CK) (::76))
+ (SETUP (posedge D) (posedge CK) (::135))
)
)
(CELL
(CELLTYPE "DFFRHQX1")
- (INSTANCE cnt_reg\[2\])
+ (INSTANCE rstn_sync_reg\[0\])
(DELAY
(ABSOLUTE
(PORT RN (::0.0))
(PORT CK (::0.0))
(PORT D (::0.0))
- (IOPATH RN Q () (::45))
- (IOPATH CK Q (::82) (::76))
+ (IOPATH RN Q () (::96))
+ (IOPATH CK Q (::249) (::224))
)
)
(TIMINGCHECK
- (RECREM (posedge RN) (posedge CK) (::-20) (::27))
- (SETUPHOLD (negedge D) (posedge CK) (::14) (::-1))
- (SETUPHOLD (posedge D) (posedge CK) (::23) (::-17))
+ (HOLD (posedge RN) (posedge CK) (::99))
+ (RECOVERY (posedge RN) (posedge CK) (::0.0))
)
)
(CELL
- (CELLTYPE "OAI31X1")
- (INSTANCE g333__7837)
+ (CELLTYPE "DFFRHQX1")
+ (INSTANCE cnt_reg\[3\])
(DELAY
(ABSOLUTE
- (PORT A0 (::0.0))
- (PORT A1 (::0.0))
- (PORT A2 (::0.0))
- (PORT B0 (::0.0))
- (IOPATH A0 Y (::57) (::48))
- (IOPATH B0 Y (::27) (::44))
- (IOPATH A1 Y (::51) (::38))
- (IOPATH A2 Y (::52) (::35))
+ (PORT RN (::0.0))
+ (PORT CK (::0.0))
+ (PORT D (::0.0))
+ (IOPATH RN Q () (::151))
+ (IOPATH CK Q (::307) (::290))
)
)
+ (TIMINGCHECK
+ (HOLD (posedge RN) (posedge CK) (::91))
+ (RECOVERY (posedge RN) (posedge CK) (::0.0))
+ (HOLD (negedge D) (posedge CK) (::0.0))
+ (HOLD (posedge D) (posedge CK) (::0.0))
+ (SETUP (negedge D) (posedge CK) (::127))
+ (SETUP (posedge D) (posedge CK) (::210))
+ )
)
(CELL
- (CELLTYPE "XNOR2X1")
- (INSTANCE g336__7557)
+ (CELLTYPE "SDFFRHQX1")
+ (INSTANCE cnt_reg\[2\])
(DELAY
(ABSOLUTE
- (PORT A (::0.0))
- (PORT B (::0.0))
- (IOPATH A Y (::52) (::53))
- (IOPATH B Y (::45) (::43))
+ (PORT RN (::0.0))
+ (PORT CK (::0.0))
+ (PORT D (::0.0))
+ (PORT SI (::0.0))
+ (PORT SE (::0.0))
+ (IOPATH RN Q () (::148))
+ (IOPATH CK Q (::307) (::287))
+ )
+ )
+ (TIMINGCHECK
+ (HOLD (posedge RN) (posedge CK) (::91))
+ (RECOVERY (posedge RN) (posedge CK) (::0.0))
+ (HOLD (negedge D) (posedge CK) (::0.0))
+ (HOLD (posedge D) (posedge CK) (::0.0))
+ (SETUP (negedge D) (posedge CK) (::166))
+ (SETUP (posedge D) (posedge CK) (::242))
+ (HOLD (negedge SI) (posedge CK) (::0.0))
+ (HOLD (posedge SI) (posedge CK) (::0.0))
+ (SETUP (negedge SI) (posedge CK) (::254))
+ (SETUP (posedge SI) (posedge CK) (::266))
+ (HOLD (negedge SE) (posedge CK) (::0.0))
+ (HOLD (posedge SE) (posedge CK) (::0.0))
+ (SETUP (negedge SE) (posedge CK) (::278))
+ (SETUP (posedge SE) (posedge CK) (::246))
+ )
+ )
+ (CELL
+ (CELLTYPE "OAI31X1")
+ (INSTANCE g337__8780)
+ (DELAY
+ (ABSOLUTE
+ (PORT A0 (::0.0))
+ (PORT A1 (::0.0))
+ (PORT A2 (::0.0))
+ (PORT B0 (::0.0))
+ (IOPATH A0 Y (::250) (::223))
+ (IOPATH B0 Y (::141) (::207))
+ (IOPATH A1 Y (::187) (::153))
+ (IOPATH A2 Y (::263) (::184))
)
)
)
@@ -84,45 +126,40 @@
(PORT D (::0.0))
(PORT SI (::0.0))
(PORT SE (::0.0))
- (IOPATH RN Q () (::54))
- (IOPATH CK Q (::91) (::85))
+ (IOPATH RN Q () (::183))
+ (IOPATH CK Q (::336) (::322))
)
)
(TIMINGCHECK
- (RECREM (posedge RN) (posedge CK) (::-20) (::27))
- (SETUPHOLD (negedge D) (posedge CK) (::41) (::-26))
- (SETUPHOLD (posedge D) (posedge CK) (::52) (::-43))
- (SETUPHOLD (negedge SI) (posedge CK) (::34) (::-20))
- (SETUPHOLD (posedge SI) (posedge CK) (::43) (::-35))
- (SETUPHOLD (negedge SE) (posedge CK) (::44) (::-13))
- (SETUPHOLD (posedge SE) (posedge CK) (::38) (::-22))
+ (HOLD (posedge RN) (posedge CK) (::91))
+ (RECOVERY (posedge RN) (posedge CK) (::0.0))
+ (HOLD (negedge D) (posedge CK) (::0.0))
+ (HOLD (posedge D) (posedge CK) (::0.0))
+ (SETUP (negedge D) (posedge CK) (::240))
+ (SETUP (posedge D) (posedge CK) (::301))
+ (HOLD (negedge SI) (posedge CK) (::0.0))
+ (HOLD (posedge SI) (posedge CK) (::0.0))
+ (SETUP (negedge SI) (posedge CK) (::178))
+ (SETUP (posedge SI) (posedge CK) (::256))
+ (HOLD (negedge SE) (posedge CK) (::0.0))
+ (HOLD (posedge SE) (posedge CK) (::0.0))
+ (SETUP (negedge SE) (posedge CK) (::230))
+ (SETUP (posedge SE) (posedge CK) (::196))
)
)
(CELL
(CELLTYPE "AOI22X1")
- (INSTANCE g335__7654)
+ (INSTANCE g339__4296)
(DELAY
(ABSOLUTE
(PORT A0 (::0.0))
(PORT A1 (::0.0))
(PORT B0 (::0.0))
(PORT B1 (::0.0))
- (IOPATH A0 Y (::47) (::48))
- (IOPATH B0 Y (::50) (::45))
- (IOPATH A1 Y (::42) (::44))
- (IOPATH B1 Y (::33) (::30))
- )
- )
- )
- (CELL
- (CELLTYPE "NAND2X1")
- (INSTANCE g339__8867)
- (DELAY
- (ABSOLUTE
- (PORT A (::0.0))
- (PORT B (::0.0))
- (IOPATH A Y (::38) (::52))
- (IOPATH B Y (::26) (::40))
+ (IOPATH A0 Y (::209) (::224))
+ (IOPATH B0 Y (::223) (::217))
+ (IOPATH A1 Y (::193) (::203))
+ (IOPATH B1 Y (::132) (::136))
)
)
)
@@ -134,159 +171,152 @@
(PORT RN (::0.0))
(PORT CK (::0.0))
(PORT D (::0.0))
- (IOPATH RN Q () (::37))
- (IOPATH CK Q (::73) (::67))
+ (IOPATH RN Q () (::136))
+ (IOPATH CK Q (::295) (::275))
)
)
(TIMINGCHECK
- (RECREM (posedge RN) (posedge CK) (::-20) (::27))
- (SETUPHOLD (negedge D) (posedge CK) (::13) (::-1))
- (SETUPHOLD (posedge D) (posedge CK) (::23) (::-17))
+ (HOLD (posedge RN) (posedge CK) (::91))
+ (RECOVERY (posedge RN) (posedge CK) (::0.0))
+ (HOLD (negedge D) (posedge CK) (::0.0))
+ (HOLD (posedge D) (posedge CK) (::0.0))
+ (SETUP (negedge D) (posedge CK) (::83))
+ (SETUP (posedge D) (posedge CK) (::164))
)
)
(CELL
- (CELLTYPE "OAI21X1")
- (INSTANCE g338__1377)
+ (CELLTYPE "INVX1")
+ (INSTANCE g341)
(DELAY
(ABSOLUTE
- (PORT A0 (::0.0))
- (PORT A1 (::0.0))
- (PORT B0 (::0.0))
- (IOPATH A0 Y (::46) (::49))
- (IOPATH B0 Y (::22) (::37))
- (IOPATH A1 Y (::33) (::30))
+ (PORT A (::0.0))
+ (IOPATH A Y (::182) (::122))
)
)
)
(CELL
- (CELLTYPE "NOR2X1")
- (INSTANCE g342__3717)
+ (CELLTYPE "OAI21X1")
+ (INSTANCE g342__3772)
(DELAY
(ABSOLUTE
- (PORT A (::0.0))
- (PORT B (::0.0))
- (IOPATH A Y (::42) (::37))
- (IOPATH B Y (::29) (::20))
+ (PORT A0 (::0.0))
+ (PORT A1 (::0.0))
+ (PORT B0 (::0.0))
+ (IOPATH A0 Y (::218) (::236))
+ (IOPATH B0 Y (::70) (::138))
+ (IOPATH A1 Y (::121) (::134))
)
)
)
(CELL
- (CELLTYPE "ADDHX1")
- (INSTANCE g340__4599)
+ (CELLTYPE "NAND2X1")
+ (INSTANCE g343__1474)
(DELAY
(ABSOLUTE
(PORT A (::0.0))
(PORT B (::0.0))
- (IOPATH A CO (::49) (::39))
- (IOPATH B CO (::42) (::33))
- (IOPATH A S (::50) (::54))
- (IOPATH B S (::34) (::42))
+ (IOPATH A Y (::202) (::280))
+ (IOPATH B Y (::98) (::185))
)
)
)
(CELL
- (CELLTYPE "AND2X1")
- (INSTANCE g344__3779)
+ (CELLTYPE "NOR2X1")
+ (INSTANCE g344__4547)
(DELAY
(ABSOLUTE
(PORT A (::0.0))
(PORT B (::0.0))
- (IOPATH A Y (::40) (::32))
- (IOPATH B Y (::46) (::36))
+ (IOPATH A Y (::204) (::171))
+ (IOPATH B Y (::118) (::87))
)
)
)
(CELL
- (CELLTYPE "DFFRHQX1")
- (INSTANCE rstn_sync_reg\[1\])
+ (CELLTYPE "AOI2BB1X1")
+ (INSTANCE g345__9682)
(DELAY
(ABSOLUTE
- (PORT RN (::0.0))
- (PORT CK (::0.0))
- (PORT D (::0.0))
- (IOPATH RN Q () (::20))
- (IOPATH CK Q (::53) (::49))
+ (PORT A0N (::0.0))
+ (PORT A1N (::0.0))
+ (PORT B0 (::0.0))
+ (IOPATH A1N Y (::172) (::178))
+ (IOPATH B0 Y (::113) (::79))
+ (IOPATH A0N Y (::131) (::136))
)
)
- (TIMINGCHECK
- (RECREM (posedge RN) (posedge CK) (::-18) (::28))
- (SETUPHOLD (negedge D) (posedge CK) (::13) (::-1))
- (SETUPHOLD (posedge D) (posedge CK) (::23) (::-17))
- )
)
(CELL
- (CELLTYPE "INVX1")
- (INSTANCE g348)
+ (CELLTYPE "AND2X1")
+ (INSTANCE g346__2683)
(DELAY
(ABSOLUTE
(PORT A (::0.0))
- (IOPATH A Y (::27) (::29))
+ (PORT B (::0.0))
+ (IOPATH A Y (::169) (::119))
+ (IOPATH B Y (::227) (::176))
)
)
)
(CELL
- (CELLTYPE "DFFRHQX1")
- (INSTANCE rstn_sync_reg\[0\])
+ (CELLTYPE "CLKAND2X3")
+ (INSTANCE g347__1309)
(DELAY
(ABSOLUTE
- (PORT RN (::0.0))
- (PORT CK (::0.0))
- (PORT D (::0.0))
- (IOPATH RN Q () (::28))
- (IOPATH CK Q (::60) (::56))
+ (PORT A (::0.0))
+ (PORT B (::0.0))
+ (IOPATH A Y (::117) (::111))
+ (IOPATH B Y (::155) (::163))
)
)
- (TIMINGCHECK
- (RECREM (posedge RN) (posedge CK) (::-18) (::28))
- )
)
(CELL
- (CELLTYPE "INVX1")
- (INSTANCE g351)
+ (CELLTYPE "INVX3")
+ (INSTANCE g348)
(DELAY
(ABSOLUTE
(PORT A (::0.0))
- (IOPATH A Y (::31) (::33))
+ (IOPATH A Y (::109) (::109))
)
)
)
(CELL
- (CELLTYPE "BUFX20")
- (INSTANCE fopt)
+ (CELLTYPE "CLKBUFX20")
+ (INSTANCE drc_bufs351)
(DELAY
(ABSOLUTE
(PORT A (::0.0))
- (IOPATH A Y (::249) (::259))
+ (IOPATH A Y (::479) (::558))
)
)
)
(CELL
- (CELLTYPE "BUFX20")
- (INSTANCE fopt400)
+ (CELLTYPE "CLKBUFX20")
+ (INSTANCE drc_bufs354)
(DELAY
(ABSOLUTE
(PORT A (::0.0))
- (IOPATH A Y (::245) (::256))
+ (IOPATH A Y (::452) (::529))
)
)
)
(CELL
- (CELLTYPE "BUFX20")
- (INSTANCE fopt403)
+ (CELLTYPE "CLKBUFX20")
+ (INSTANCE drc_bufs357)
(DELAY
(ABSOLUTE
(PORT A (::0.0))
- (IOPATH A Y (::249) (::259))
+ (IOPATH A Y (::452) (::527))
)
)
)
(CELL
- (CELLTYPE "BUFX20")
- (INSTANCE fopt406)
+ (CELLTYPE "CLKBUFX20")
+ (INSTANCE drc_bufs360)
(DELAY
(ABSOLUTE
(PORT A (::0.0))
- (IOPATH A Y (::254) (::262))
+ (IOPATH A Y (::441) (::516))
)
)
)
diff --git a/compteur/implementation/syn/netlist/compteur.syn.v b/compteur/implementation/syn/netlist/compteur.syn.v
index af80e8c65e6dc0445895e3c3cfc4fac7ae19e31b..1f1c14c41effe48dffa145ec4780849a725fb625 100644
--- a/compteur/implementation/syn/netlist/compteur.syn.v
+++ b/compteur/implementation/syn/netlist/compteur.syn.v
@@ -1,6 +1,6 @@
-// Generated by Cadence Genus(TM) Synthesis Solution 17.10-p007_1
-// Generated on: Sep 10 2019 10:42:42 EDT (Sep 10 2019 14:42:42 UTC)
+// Generated by Cadence Genus(TM) Synthesis Solution 18.10-p003_1
+// Generated on: Oct 2 2019 14:33:08 EDT (Oct 2 2019 18:33:08 UTC)
// Verification Directory fv/compteur
@@ -10,36 +10,35 @@ module compteur(i_clk, i_rstn, i_en, o_cnt);
wire i_clk, i_rstn, i_en;
wire [3:0] o_cnt;
wire [1:0] rstn_sync;
- wire [3:0] cnt;
- wire n_1, n_3, n_8, n_9, n_11, n_12, n_13, n_16;
- wire n_17, n_18, n_19;
- DFFRHQX1 \cnt_reg[3] (.RN (rstn_sync[1]), .CK (i_clk), .D (n_19), .Q
- (cnt[3]));
- DFFRHQX1 \cnt_reg[2] (.RN (rstn_sync[1]), .CK (i_clk), .D (n_18), .Q
- (cnt[2]));
- OAI31X1 g333__7837(.A0 (cnt[3]), .A1 (n_3), .A2 (n_17), .B0 (n_16),
- .Y (n_19));
- XNOR2X1 g336__7557(.A (n_17), .B (cnt[2]), .Y (n_18));
- SDFFRHQX1 \cnt_reg[1] (.RN (rstn_sync[1]), .CK (i_clk), .D (cnt[1]),
- .SI (n_11), .SE (n_13), .Q (cnt[1]));
- AOI22X1 g335__7654(.A0 (cnt[3]), .A1 (n_12), .B0 (cnt[1]), .B1 (n_9),
- .Y (n_16));
- NAND2X1 g339__8867(.A (cnt[1]), .B (n_13), .Y (n_17));
- DFFRHQX1 \cnt_reg[0] (.RN (rstn_sync[1]), .CK (i_clk), .D (n_8), .Q
- (cnt[0]));
- OAI21X1 g338__1377(.A0 (cnt[1]), .A1 (n_1), .B0 (n_13), .Y (n_12));
- NOR2X1 g342__3717(.A (cnt[1]), .B (n_9), .Y (n_11));
- ADDHX1 g340__4599(.A (cnt[0]), .B (i_en), .CO (n_13), .S (n_8));
- AND2X1 g344__3779(.A (n_3), .B (cnt[3]), .Y (n_9));
+ wire n_0, n_1, n_2, n_3, n_4, n_5, n_6, n_7;
+ wire n_8, n_9, n_10, n_11, n_12, n_13;
DFFRHQX1 \rstn_sync_reg[1] (.RN (i_rstn), .CK (i_clk), .D
(rstn_sync[0]), .Q (rstn_sync[1]));
- INVX1 g348(.A (cnt[2]), .Y (n_1));
DFFRHQX1 \rstn_sync_reg[0] (.RN (i_rstn), .CK (i_clk), .D (1'b1), .Q
(rstn_sync[0]));
- INVX1 g351(.A (cnt[2]), .Y (n_3));
- BUFX20 fopt(.A (cnt[2]), .Y (o_cnt[2]));
- BUFX20 fopt400(.A (cnt[0]), .Y (o_cnt[0]));
- BUFX20 fopt403(.A (cnt[3]), .Y (o_cnt[3]));
- BUFX20 fopt406(.A (cnt[1]), .Y (o_cnt[1]));
+ DFFRHQX1 \cnt_reg[3] (.RN (rstn_sync[1]), .CK (i_clk), .D (n_9), .Q
+ (n_13));
+ SDFFRHQX1 \cnt_reg[2] (.RN (rstn_sync[1]), .CK (i_clk), .D (n_6), .SI
+ (n_7), .SE (n_12), .Q (n_12));
+ OAI31X1 g337__8780(.A0 (n_13), .A1 (n_0), .A2 (n_7), .B0 (n_8), .Y
+ (n_9));
+ SDFFRHQX1 \cnt_reg[1] (.RN (rstn_sync[1]), .CK (i_clk), .D (n_11),
+ .SI (n_4), .SE (n_1), .Q (n_11));
+ AOI22X1 g339__4296(.A0 (n_13), .A1 (n_5), .B0 (n_11), .B1 (n_2), .Y
+ (n_8));
+ DFFRHQX1 \cnt_reg[0] (.RN (rstn_sync[1]), .CK (i_clk), .D (n_3), .Q
+ (n_10));
+ INVX1 g341(.A (n_7), .Y (n_6));
+ OAI21X1 g342__3772(.A0 (n_11), .A1 (n_0), .B0 (n_1), .Y (n_5));
+ NAND2X1 g343__1474(.A (n_11), .B (n_1), .Y (n_7));
+ NOR2X1 g344__4547(.A (n_11), .B (n_2), .Y (n_4));
+ AOI2BB1X1 g345__9682(.A0N (i_en), .A1N (n_10), .B0 (n_1), .Y (n_3));
+ AND2X1 g346__2683(.A (n_0), .B (n_13), .Y (n_2));
+ CLKAND2X3 g347__1309(.A (i_en), .B (n_10), .Y (n_1));
+ INVX3 g348(.A (n_12), .Y (n_0));
+ CLKBUFX20 drc_bufs351(.A (n_11), .Y (o_cnt[1]));
+ CLKBUFX20 drc_bufs354(.A (n_13), .Y (o_cnt[3]));
+ CLKBUFX20 drc_bufs357(.A (n_12), .Y (o_cnt[2]));
+ CLKBUFX20 drc_bufs360(.A (n_10), .Y (o_cnt[0]));
endmodule
diff --git a/compteur/implementation/syn/reports/compteur.check.rpt b/compteur/implementation/syn/reports/compteur.check.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..527cadeed3878f314015b827ecf678f99b2f03fa
--- /dev/null
+++ b/compteur/implementation/syn/reports/compteur.check.rpt
@@ -0,0 +1,615 @@
+
+ Check Design Report
+ --------------------
+
+ Long Module Names
+----------------------
+No subdesign's name is greater than 1.5k in length.
+
+ Unresolved References & Empty Modules
+ -------------------------------------
+No unresolved references in design 'compteur'
+
+No empty modules in design 'compteur'
+
+ Unloaded Pin(s), Port(s)
+ -------------------------
+No unloaded sequential element in 'compteur'
+
+No unloaded port in 'compteur'
+
+ Unloaded Combinational Pin(s)
+ -------------------------------
+No unloaded combinational element in 'compteur'
+
+ Assigns
+ -------
+Total number of assign statements in design 'compteur' : 0
+
+ Undriven Port(s)/Pin(s)
+ ------------------------
+No undriven combinational pin in 'compteur'
+
+No undriven sequential pin in 'compteur'
+
+No undriven hierarchical pin in 'compteur'
+
+No undriven port in 'compteur'
+
+ Multidriven Port(s)/Pin(s)
+--------------------------
+
+No multidriven combinational pin in 'compteur'
+
+No multidriven sequential pin in 'compteur'
+
+No multidriven hierarchical pin in 'compteur'
+
+No multidriven ports in 'compteur'
+
+No multidriven unloaded nets in 'compteur'
+
+ Constant Pin(s)
+ ----------------
+No constant combinational pin(s) in design 'compteur'
+
+No constant sequential pin(s) in design 'compteur'
+
+design 'compteur' has the following constant input hierarchical pin(s)
+hpin:compteur/add_57_22/B (fanout : 2)
+hpin:compteur/mux_rstn_sync_39_16/in_1[0] (fanout : 1)
+hpin:compteur/mux_rstn_sync_39_16/in_1[1] (fanout : 1)
+hpin:compteur/mux_cnt_54_17/in_1[0] (fanout : 1)
+hpin:compteur/mux_cnt_54_17/in_1[1] (fanout : 1)
+hpin:compteur/mux_cnt_54_17/in_1[2] (fanout : 1)
+hpin:compteur/mux_cnt_54_17/in_1[3] (fanout : 1)
+hpin:compteur/mux_cnt_50_14/in_1[0] (fanout : 1)
+hpin:compteur/mux_cnt_50_14/in_1[1] (fanout : 1)
+hpin:compteur/mux_cnt_50_14/in_1[2] (fanout : 1)
+hpin:compteur/mux_cnt_50_14/in_1[3] (fanout : 1)
+hpin:compteur/mux_rstn_sync_39_16/in_0[0] (fanout : 1)
+Total number of constant hierarchical pins in design 'compteur' : 12
+
+No constant connected ports in design 'compteur'
+
+ Preserved instances(s)
+ ----------------
+No preserved combinational instance(s) in design 'compteur'
+No preserved sequential instance(s) in design 'compteur'
+No preserved hierarchical instance(s) in design 'compteur'
+
+ Physical only instances(s)
+ ----------------
+No physical only instance(s) in design 'compteur'
+
+ Logical only instance(s) and linked libcells
+ -----------------------------------------
+No logical only instance(s) in design 'compteur'
+
+Libcells with no corresponding LEF
+----------------------------------
+lib_cell:default_emulate_libset_max/slow_vdd1v0/ACHCONX2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/ADDFHX1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/ADDFHX2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/ADDFHX4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/ADDFHXL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/ADDFX1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/ADDFX2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/ADDFX4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/ADDFXL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/ADDHX1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/ADDHX2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/ADDHX4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/ADDHXL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AND2X1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AND2X2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AND2X4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AND2X6
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AND2X8
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AND2XL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AND3X1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AND3X2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AND3X4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AND3X6
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AND3X8
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AND3XL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AND4X1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AND4X2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AND4X4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AND4X6
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AND4X8
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AND4XL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/ANTENNA
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AO21X1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AO21X2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AO21X4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AO21XL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AO22X1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AO22X2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AO22X4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AO22XL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI211X1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI211X2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI211X4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI211XL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI21X1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI21X2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI21X4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI21XL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI221X1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI221X2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI221X4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI221XL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI222X1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI222X2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI222X4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI222XL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI22X1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI22X2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI22X4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI22XL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI2BB1X1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI2BB1X2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI2BB1X4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI2BB1XL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI2BB2X1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI2BB2X2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI2BB2X4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI2BB2XL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI31X1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI31X2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI31X4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI31XL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI32X1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI32X2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI32X4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI32XL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI33X1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI33X2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI33X4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/AOI33XL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/BMXIX2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/BMXIX4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/BUFX12
+lib_cell:default_emulate_libset_max/slow_vdd1v0/BUFX16
+lib_cell:default_emulate_libset_max/slow_vdd1v0/BUFX2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/BUFX20
+lib_cell:default_emulate_libset_max/slow_vdd1v0/BUFX3
+lib_cell:default_emulate_libset_max/slow_vdd1v0/BUFX4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/BUFX6
+lib_cell:default_emulate_libset_max/slow_vdd1v0/BUFX8
+lib_cell:default_emulate_libset_max/slow_vdd1v0/CLKAND2X12
+lib_cell:default_emulate_libset_max/slow_vdd1v0/CLKAND2X2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/CLKAND2X3
+lib_cell:default_emulate_libset_max/slow_vdd1v0/CLKAND2X4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/CLKAND2X6
+lib_cell:default_emulate_libset_max/slow_vdd1v0/CLKAND2X8
+lib_cell:default_emulate_libset_max/slow_vdd1v0/CLKBUFX12
+lib_cell:default_emulate_libset_max/slow_vdd1v0/CLKBUFX16
+lib_cell:default_emulate_libset_max/slow_vdd1v0/CLKBUFX2
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+lib_cell:default_emulate_libset_max/slow_vdd1v0/OR4X8
+lib_cell:default_emulate_libset_max/slow_vdd1v0/OR4XL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFHQX1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFHQX2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFHQX4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFHQX8
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFNSRX1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFNSRX2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFNSRX4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFNSRXL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFQX1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFQX2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFQX4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFQXL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFRHQX1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFRHQX2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFRHQX4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFRHQX8
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFRX1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFRX2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFRX4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFRXL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSHQX1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSHQX2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSHQX4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSHQX8
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSRHQX1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSRHQX2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSRHQX4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSRHQX8
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSRX1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSRX2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSRX4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSRXL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSX1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSX2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSX4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFSXL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFTRX1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFTRX2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFTRX4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFTRXL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFX1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFX2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFX4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SDFFXL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SEDFFHQX1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SEDFFHQX2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SEDFFHQX4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SEDFFHQX8
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SEDFFTRX1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SEDFFTRX2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SEDFFTRX4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SEDFFTRXL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SEDFFX1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SEDFFX2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SEDFFX4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SEDFFXL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SMDFFHQX1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SMDFFHQX2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SMDFFHQX4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/SMDFFHQX8
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TBUFX1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TBUFX12
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TBUFX16
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TBUFX2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TBUFX20
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TBUFX3
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TBUFX4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TBUFX6
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TBUFX8
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TBUFXL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TIEHI
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TIELO
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNCAX12
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNCAX16
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNCAX2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNCAX20
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNCAX3
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNCAX4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNCAX6
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNCAX8
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNSRX1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNSRX2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNSRX4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNSRXL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNTSCAX12
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNTSCAX16
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNTSCAX2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNTSCAX20
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNTSCAX3
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNTSCAX4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNTSCAX6
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNTSCAX8
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNX1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNX2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNX4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATNXL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATSRX1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATSRX2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATSRX4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATSRXL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATX1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATX2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATX4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/TLATXL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/XNOR2X1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/XNOR2X2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/XNOR2X4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/XNOR2XL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/XNOR3X1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/XNOR3XL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/XOR2X1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/XOR2X2
+lib_cell:default_emulate_libset_max/slow_vdd1v0/XOR2X4
+lib_cell:default_emulate_libset_max/slow_vdd1v0/XOR2XL
+lib_cell:default_emulate_libset_max/slow_vdd1v0/XOR3X1
+lib_cell:default_emulate_libset_max/slow_vdd1v0/XOR3XL
+
+Total number of cell(s) with only library (.lib) info : 489
+
+LEF cells with no corresponding libcell
+---------------------------------------
+
+No physical (LEF) cells found.
+
+ Summary
+ -------
+
+ Name Total
+-------------------------------------------
+Unresolved References 0
+Empty Modules 0
+Unloaded Port(s) 0
+Unloaded Sequential Pin(s) 0
+Unloaded Combinational Pin(s) 0
+Assigns 0
+Undriven Port(s) 0
+Undriven Leaf Pin(s) 0
+Undriven hierarchical pin(s) 0
+Multidriven Port(s) 0
+Multidriven Leaf Pin(s) 0
+Multidriven hierarchical Pin(s) 0
+Multidriven unloaded net(s) 0
+Constant Port(s) 0
+Constant Leaf Pin(s) 0
+Constant hierarchical Pin(s) 12
+Preserved leaf instance(s) 0
+Preserved hierarchical instance(s) 0
+Libcells with no LEF cell 489
+Physical (LEF) cells with no libcell 0
+Subdesigns with long module name 0
+Physical only instance(s) 0
+Logical only instance(s) 0
diff --git a/compteur/implementation/syn/reports/compteur.clk.rpt b/compteur/implementation/syn/reports/compteur.clk.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..bf05d87fcdaeb75ed2abda2464f7cebe23a7ce89
--- /dev/null
+++ b/compteur/implementation/syn/reports/compteur.clk.rpt
@@ -0,0 +1,45 @@
+============================================================
+ Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
+ Generated on: Oct 02 2019 02:33:05 pm
+ Module: compteur
+ Technology library: slow_vdd1v0 1.0
+ Operating conditions: PVT_0P9V_125C
+ Interconnect mode: global
+ Area mode: timing library
+============================================================
+
+
+ Clock Description
+ -----------------
+
+ Clock Clock Source No of
+ Name Period Rise Fall Domain Pin/Port Registers
+-------------------------------------------------------------
+ clk 1250.0 0.0 625.0 domain_1 i_clk 6
+
+ Clock Network Latency / Setup Uncertainty
+ -----------------------------------------
+
+ Network Network Source Source Setup Setup
+Clock Latency Latency Latency Latency Uncertainty Uncertainty
+ Name Rise Fall Rise Fall Rise Fall
+----------------------------------------------------------------------
+clk 0.0 0.0 0.0 0.0 100.0 100.0
+
+ Clock Relationship (with uncertainty & latency)
+ -----------------------------------------------
+
+ From To R->R R->F F->R F->F
+-----------------------------------------------
+ clk clk 1150.0 525.0 525.0 1150.0
+============================================================
+ Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
+ Generated on: Oct 02 2019 02:33:05 pm
+ Module: compteur
+ Technology library: slow_vdd1v0 1.0
+ Operating conditions: PVT_0P9V_125C
+ Interconnect mode: global
+ Area mode: timing library
+============================================================
+
+No clocks to report
diff --git a/compteur/implementation/syn/reports/compteur.gen.area.rpt b/compteur/implementation/syn/reports/compteur.gen.area.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..784ce004b1c2792a5300708a2ab745d2e8247774
--- /dev/null
+++ b/compteur/implementation/syn/reports/compteur.gen.area.rpt
@@ -0,0 +1,12 @@
+============================================================
+ Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
+ Generated on: Oct 02 2019 02:33:06 pm
+ Module: compteur
+ Operating conditions: PVT_0P9V_125C
+ Interconnect mode: global
+ Area mode: timing library
+============================================================
+
+Instance Module Cell Count Cell Area Net Area Total Area
+--------------------------------------------------------------
+compteur 34 128.126 2.965 131.091
diff --git a/compteur/implementation/syn/reports/compteur.gen.gates.rpt b/compteur/implementation/syn/reports/compteur.gen.gates.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..14105c7ad0d5ba3c8e8cb0bf29cccf991d86d4f3
--- /dev/null
+++ b/compteur/implementation/syn/reports/compteur.gen.gates.rpt
@@ -0,0 +1,19 @@
+============================================================
+ Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
+ Generated on: Oct 02 2019 02:33:06 pm
+ Module: compteur
+ Operating conditions: PVT_0P9V_125C
+ Interconnect mode: global
+ Area mode: timing library
+============================================================
+
+
+ Type Instances Area Area %
+--------------------------------------
+sequential 6 0.000 0.0
+inverter 2 0.000 0.0
+logic 26 0.000 0.0
+physical_cells 0 0.000 0.0
+--------------------------------------
+total 34 0.000 0.0
+
diff --git a/compteur/implementation/syn/reports/compteur.gen.power.rpt b/compteur/implementation/syn/reports/compteur.gen.power.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..04f5023cf55aaa8a68afac856b44ac77bb978e2b
--- /dev/null
+++ b/compteur/implementation/syn/reports/compteur.gen.power.rpt
@@ -0,0 +1,14 @@
+============================================================
+ Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
+ Generated on: Oct 02 2019 02:33:06 pm
+ Module: compteur
+ Operating conditions: PVT_0P9V_125C
+ Interconnect mode: global
+ Area mode: timing library
+============================================================
+
+ Leakage Dynamic Total
+Instance Cells Power(nW) Power(nW) Power(nW)
+------------------------------------------------
+compteur 34 0.799 127636.633 127637.432
+
diff --git a/compteur/implementation/syn/reports/compteur.gen.timing.rpt b/compteur/implementation/syn/reports/compteur.gen.timing.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..f969153ff88307b9a1131d7acfe1f61b37baf73e
--- /dev/null
+++ b/compteur/implementation/syn/reports/compteur.gen.timing.rpt
@@ -0,0 +1,47 @@
+============================================================
+ Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
+ Generated on: Oct 02 2019 02:33:06 pm
+ Module: compteur
+ Operating conditions: PVT_0P9V_125C
+ Interconnect mode: global
+ Area mode: timing library
+============================================================
+
+
+Path 1: MET (146 ps) Setup Check with Pin cnt_reg[3]/clk->d
+ Group: clk
+ Startpoint: (R) cnt_reg[1]/clk
+ Clock: (R) clk
+ Endpoint: (R) cnt_reg[3]/d
+ Clock: (R) clk
+
+ Capture Launch
+ Clock Edge:+ 1250 0
+ Src Latency:+ 0 0
+ Net Latency:+ 0 (I) 0 (I)
+ Arrival:= 1250 0
+
+ Setup:- 119
+ Uncertainty:- 100
+ Required Time:= 1031
+ Launch Clock:- 0
+ Data Path:- 885
+ Slack:= 146
+
+#--------------------------------------------------------------------------------------------------
+# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance
+# (fF) (ps) (ps) (ps) Location
+#--------------------------------------------------------------------------------------------------
+ cnt_reg[1]/clk - - R (arrival) 6 - 0 - 0 (-,-)
+ cnt_reg[1]/q (u) clk->q F unmapped_d_flop 6 506.6 0 454 454 (-,-)
+ g173/z (u) in_1->z R unmapped_nand2 2 2.0 0 79 533 (-,-)
+ g162/z (u) in_0->z R unmapped_complex2 2 2.0 0 79 611 (-,-)
+ g160/z (u) in_0->z F unmapped_nand2 1 1.0 0 68 680 (-,-)
+ g154/z (u) in_1->z R unmapped_nand2 1 1.0 0 68 748 (-,-)
+ g152/z (u) in_0->z F unmapped_nand2 1 1.0 0 68 816 (-,-)
+ g151/z (u) in_0->z R unmapped_nand2 1 1.0 0 68 885 (-,-)
+ cnt_reg[3]/d <<< - R unmapped_d_flop 1 - - 0 885 (-,-)
+#--------------------------------------------------------------------------------------------------
+
+(u) : Net has unmapped pin(s).
+
diff --git a/compteur/implementation/syn/reports/compteur.hier_elab.rpt b/compteur/implementation/syn/reports/compteur.hier_elab.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..5a8e93298eb02ca8a35aaeb1f947700d4bcf6078
--- /dev/null
+++ b/compteur/implementation/syn/reports/compteur.hier_elab.rpt
@@ -0,0 +1,17 @@
+============================================================
+ Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
+ Generated on: Oct 02 2019 02:33:05 pm
+ Module: compteur
+ Technology library: slow_vdd1v0 1.0
+ Operating conditions: PVT_0P9V_125C
+ Interconnect mode: global
+ Area mode: timing library
+============================================================
+
+ Instance Cell Count TNS Cells(same hier) TNS(same hier)
+-------------------------------------------------------------------------
+compteur 35 0 0 0
+ add_57_22 13 0 0
+ mux_cnt_50_14 4 0 0
+ mux_cnt_54_17 4 0 0
+ mux_rstn_sync_39_16 2 0 0
diff --git a/compteur/implementation/syn/reports/compteur.map.area.rpt b/compteur/implementation/syn/reports/compteur.map.area.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..594b12271de83ff742b8f29e282166f37cd9bc25
--- /dev/null
+++ b/compteur/implementation/syn/reports/compteur.map.area.rpt
@@ -0,0 +1,12 @@
+============================================================
+ Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
+ Generated on: Oct 02 2019 02:33:07 pm
+ Module: compteur
+ Operating conditions: PVT_0P9V_125C
+ Interconnect mode: global
+ Area mode: timing library
+============================================================
+
+Instance Module Cell Count Cell Area Net Area Total Area
+--------------------------------------------------------------
+compteur 20 90.972 22.408 113.380
diff --git a/compteur/implementation/syn/reports/compteur.map.gates.rpt b/compteur/implementation/syn/reports/compteur.map.gates.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..4e64e91d16365cc52a1a388e48d6854023b25353
--- /dev/null
+++ b/compteur/implementation/syn/reports/compteur.map.gates.rpt
@@ -0,0 +1,40 @@
+============================================================
+ Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
+ Generated on: Oct 02 2019 02:33:07 pm
+ Module: compteur
+ Operating conditions: PVT_0P9V_125C
+ Interconnect mode: global
+ Area mode: timing library
+============================================================
+
+
+ Gate Instances Area Library
+--------------------------------------------
+AND2X1 1 1.368 slow_vdd1v0
+AOI22X1 1 2.052 slow_vdd1v0
+AOI2BB1X1 1 2.052 slow_vdd1v0
+CLKAND2X3 1 3.078 slow_vdd1v0
+CLKBUFX20 4 32.832 slow_vdd1v0
+DFFRHQX1 4 24.624 slow_vdd1v0
+INVX1 1 0.684 slow_vdd1v0
+INVX3 1 1.368 slow_vdd1v0
+NAND2X2 1 1.710 slow_vdd1v0
+NOR2X1 1 1.026 slow_vdd1v0
+OAI21X1 1 1.710 slow_vdd1v0
+OAI31X1 1 2.052 slow_vdd1v0
+SDFFRHQX1 2 16.416 slow_vdd1v0
+--------------------------------------------
+total 20 90.972
+
+
+
+ Type Instances Area Area %
+---------------------------------------
+sequential 6 41.040 45.1
+inverter 2 2.052 2.3
+buffer 4 32.832 36.1
+logic 8 15.048 16.5
+physical_cells 0 0.000 0.0
+---------------------------------------
+total 20 90.972 100.0
+
diff --git a/compteur/implementation/syn/reports/compteur.map.power.rpt b/compteur/implementation/syn/reports/compteur.map.power.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..451a3f2181b0e99e1c23d129606fdf81285c2190
--- /dev/null
+++ b/compteur/implementation/syn/reports/compteur.map.power.rpt
@@ -0,0 +1,14 @@
+============================================================
+ Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
+ Generated on: Oct 02 2019 02:33:07 pm
+ Module: compteur
+ Operating conditions: PVT_0P9V_125C
+ Interconnect mode: global
+ Area mode: timing library
+============================================================
+
+ Leakage Dynamic Total
+Instance Cells Power(nW) Power(nW) Power(nW)
+------------------------------------------------
+compteur 20 3.850 321043.714 321047.564
+
diff --git a/compteur/implementation/syn/reports/compteur.map.timing.rpt b/compteur/implementation/syn/reports/compteur.map.timing.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..6a8d199122ab28b7490040b6d366e663420091e9
--- /dev/null
+++ b/compteur/implementation/syn/reports/compteur.map.timing.rpt
@@ -0,0 +1,43 @@
+============================================================
+ Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
+ Generated on: Oct 02 2019 02:33:07 pm
+ Module: compteur
+ Operating conditions: PVT_0P9V_125C
+ Interconnect mode: global
+ Area mode: timing library
+============================================================
+
+
+Path 1: MET (32 ps) Setup Check with Pin cnt_reg[3]/CK->D
+ Group: clk
+ Startpoint: (R) cnt_reg[0]/CK
+ Clock: (R) clk
+ Endpoint: (F) cnt_reg[3]/D
+ Clock: (R) clk
+
+ Capture Launch
+ Clock Edge:+ 1250 0
+ Src Latency:+ 0 0
+ Net Latency:+ 0 (I) 0 (I)
+ Arrival:= 1250 0
+
+ Setup:- 127
+ Uncertainty:- 100
+ Required Time:= 1023
+ Launch Clock:- 0
+ Data Path:- 991
+ Slack:= 32
+
+#---------------------------------------------------------------------------------------
+# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance
+# (fF) (ps) (ps) (ps) Location
+#---------------------------------------------------------------------------------------
+ cnt_reg[0]/CK - - R (arrival) 6 - 0 - 0 (-,-)
+ cnt_reg[0]/Q - CK->Q R DFFRHQX1 3 5.9 135 295 295 (-,-)
+ g347__1309/Y - B->Y R CLKAND2X3 4 6.2 59 156 451 (-,-)
+ g342__3772/Y - B0->Y F OAI21X1 1 2.0 166 139 590 (-,-)
+ g339__4296/Y - A1->Y R AOI22X1 1 2.0 160 193 783 (-,-)
+ g337__8780/Y - B0->Y F OAI31X1 1 1.9 172 208 991 (-,-)
+ cnt_reg[3]/D <<< - F DFFRHQX1 1 - - 0 991 (-,-)
+#---------------------------------------------------------------------------------------
+
diff --git a/compteur/implementation/syn/reports/compteur.syn.area.rpt b/compteur/implementation/syn/reports/compteur.syn.area.rpt
index 886e7ea1e7899b3bd33b8ff78547706a72fd4f01..b4c5ce752af2b69589b1aa6cff10fb9f0ca04d6a 100644
--- a/compteur/implementation/syn/reports/compteur.syn.area.rpt
+++ b/compteur/implementation/syn/reports/compteur.syn.area.rpt
@@ -1,12 +1,12 @@
============================================================
- Generated by: Genus(TM) Synthesis Solution 17.10-p007_1
- Generated on: Sep 10 2019 10:42:42 am
+ Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
+ Generated on: Oct 02 2019 02:33:08 pm
Module: compteur
- Operating conditions: PVT_1P1V_0C
+ Operating conditions: PVT_0P9V_125C
Interconnect mode: global
Area mode: timing library
============================================================
-Instance Module Cells Cell Area Net Area Total Area
----------------------------------------------------------
-compteur 20 89 22 110
+Instance Module Cell Count Cell Area Net Area Total Area
+--------------------------------------------------------------
+compteur 20 90.288 22.408 112.696
diff --git a/compteur/implementation/syn/reports/compteur.syn.gates.rpt b/compteur/implementation/syn/reports/compteur.syn.gates.rpt
index 139084c6876b9f3d121f79f920050ab8c22ae3f2..4f3621c2d91bc94d1a33a802c895ae315c14af48 100644
--- a/compteur/implementation/syn/reports/compteur.syn.gates.rpt
+++ b/compteur/implementation/syn/reports/compteur.syn.gates.rpt
@@ -1,8 +1,8 @@
============================================================
- Generated by: Genus(TM) Synthesis Solution 17.10-p007_1
- Generated on: Sep 10 2019 10:42:42 am
+ Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
+ Generated on: Oct 02 2019 02:33:08 pm
Module: compteur
- Operating conditions: PVT_1P1V_0C
+ Operating conditions: PVT_0P9V_125C
Interconnect mode: global
Area mode: timing library
============================================================
@@ -10,30 +10,31 @@
Gate Instances Area Library
--------------------------------------------
-ADDHX1 1 3.762 fast_vdd1v0
-AND2X1 1 1.368 fast_vdd1v0
-AOI22X1 1 2.052 fast_vdd1v0
-BUFX20 4 32.832 fast_vdd1v0
-DFFRHQX1 5 30.780 fast_vdd1v0
-INVX1 2 1.368 fast_vdd1v0
-NAND2X1 1 1.026 fast_vdd1v0
-NOR2X1 1 1.026 fast_vdd1v0
-OAI21X1 1 1.710 fast_vdd1v0
-OAI31X1 1 2.052 fast_vdd1v0
-SDFFRHQX1 1 8.208 fast_vdd1v0
-XNOR2X1 1 2.394 fast_vdd1v0
+AND2X1 1 1.368 slow_vdd1v0
+AOI22X1 1 2.052 slow_vdd1v0
+AOI2BB1X1 1 2.052 slow_vdd1v0
+CLKAND2X3 1 3.078 slow_vdd1v0
+CLKBUFX20 4 32.832 slow_vdd1v0
+DFFRHQX1 4 24.624 slow_vdd1v0
+INVX1 1 0.684 slow_vdd1v0
+INVX3 1 1.368 slow_vdd1v0
+NAND2X1 1 1.026 slow_vdd1v0
+NOR2X1 1 1.026 slow_vdd1v0
+OAI21X1 1 1.710 slow_vdd1v0
+OAI31X1 1 2.052 slow_vdd1v0
+SDFFRHQX1 2 16.416 slow_vdd1v0
--------------------------------------------
-total 20 88.578
+total 20 90.288
Type Instances Area Area %
---------------------------------------
-sequential 6 38.988 44.0
-inverter 2 1.368 1.5
-buffer 4 32.832 37.1
-logic 8 15.390 17.4
+sequential 6 41.040 45.5
+inverter 2 2.052 2.3
+buffer 4 32.832 36.4
+logic 8 14.364 15.9
physical_cells 0 0.000 0.0
---------------------------------------
-total 20 88.578 100.0
+total 20 90.288 100.0
diff --git a/compteur/implementation/syn/reports/compteur.syn.power.rpt b/compteur/implementation/syn/reports/compteur.syn.power.rpt
index 89770e44e1d969a252df21631297d3616cce3d32..4c2df9047fbd6f2ff567694d566669a035a7da57 100644
--- a/compteur/implementation/syn/reports/compteur.syn.power.rpt
+++ b/compteur/implementation/syn/reports/compteur.syn.power.rpt
@@ -1,14 +1,14 @@
============================================================
- Generated by: Genus(TM) Synthesis Solution 17.10-p007_1
- Generated on: Sep 10 2019 10:42:42 am
+ Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
+ Generated on: Oct 02 2019 02:33:08 pm
Module: compteur
- Operating conditions: PVT_1P1V_0C
+ Operating conditions: PVT_0P9V_125C
Interconnect mode: global
Area mode: timing library
============================================================
- Leakage Dynamic Total
-Instance Cells Power(nW) Power(nW) Power(nW)
--------------------------------------------------
-compteur 20 7.609 1066410.418 1066418.026
+ Leakage Dynamic Total
+Instance Cells Power(nW) Power(nW) Power(nW)
+------------------------------------------------
+compteur 20 3.823 320889.077 320892.900
diff --git a/compteur/implementation/syn/reports/compteur.syn.timing.rpt b/compteur/implementation/syn/reports/compteur.syn.timing.rpt
index 9756f5cd7c41eeec317cd0ec6dd109ce8c56b3bf..897129983865e3979f702ab65ddc4259e7315add 100644
--- a/compteur/implementation/syn/reports/compteur.syn.timing.rpt
+++ b/compteur/implementation/syn/reports/compteur.syn.timing.rpt
@@ -1,40 +1,43 @@
============================================================
- Generated by: Genus(TM) Synthesis Solution 17.10-p007_1
- Generated on: Sep 10 2019 10:42:42 am
+ Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
+ Generated on: Oct 02 2019 02:33:08 pm
Module: compteur
- Operating conditions: PVT_1P1V_0C
+ Operating conditions: PVT_0P9V_125C
Interconnect mode: global
Area mode: timing library
============================================================
-Path 1: MET (246 ps) Late External Delay Assertion at pin o_cnt[1]
+Path 1: MET (36 ps) Setup Check with Pin cnt_reg[3]/CK->D
Group: clk
- Startpoint: (R) cnt_reg[1]/CK
+ Startpoint: (R) cnt_reg[0]/CK
Clock: (R) clk
- Endpoint: (F) o_cnt[1]
+ Endpoint: (F) cnt_reg[3]/D
Clock: (R) clk
Capture Launch
- Clock Edge:+ 1000 0
+ Clock Edge:+ 1250 0
Src Latency:+ 0 0
Net Latency:+ 0 (I) 0 (I)
- Arrival:= 1000 0
+ Arrival:= 1250 0
- Output Delay:- 300
+ Setup:- 127
Uncertainty:- 100
- Required Time:= 600
+ Required Time:= 1023
Launch Clock:- 0
- Data Path:- 354
- Slack:= 246
+ Data Path:- 987
+ Slack:= 36
-#--------------------------------------------------------------------------------
-# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival
-# (fF) (ps) (ps) (ps)
-#--------------------------------------------------------------------------------
- cnt_reg[1]/CK - - R (arrival) 6 - 0 - 0
- cnt_reg[1]/Q - CK->Q F SDFFRHQX1 6 9.9 67 85 85
- fopt406/Y - A->Y F BUFX20 1 1001.6 392 262 347
- o_cnt[1] <<< - F (port) - - - 7 354
-#--------------------------------------------------------------------------------
+#---------------------------------------------------------------------------------------
+# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance
+# (fF) (ps) (ps) (ps) Location
+#---------------------------------------------------------------------------------------
+ cnt_reg[0]/CK - - R (arrival) 6 - 0 - 0 (-,-)
+ cnt_reg[0]/Q - CK->Q R DFFRHQX1 3 5.9 135 295 295 (-,-)
+ g347__1309/Y - B->Y R CLKAND2X3 4 5.8 56 155 449 (-,-)
+ g342__3772/Y - B0->Y F OAI21X1 1 2.0 165 138 587 (-,-)
+ g339__4296/Y - A1->Y R AOI22X1 1 2.0 159 193 780 (-,-)
+ g337__8780/Y - B0->Y F OAI31X1 1 1.9 172 207 987 (-,-)
+ cnt_reg[3]/D <<< - F DFFRHQX1 1 - - 0 987 (-,-)
+#---------------------------------------------------------------------------------------
diff --git a/compteur/implementation/syn/reports/compteur.syn.timing_lint.rpt b/compteur/implementation/syn/reports/compteur.timing_lint.rpt
similarity index 56%
rename from compteur/implementation/syn/reports/compteur.syn.timing_lint.rpt
rename to compteur/implementation/syn/reports/compteur.timing_lint.rpt
index d2e377e11b150d4d84d18afede49ec776626683b..e7adf33e6a54bb913aa9a12115709a32167f6b08 100644
--- a/compteur/implementation/syn/reports/compteur.syn.timing_lint.rpt
+++ b/compteur/implementation/syn/reports/compteur.timing_lint.rpt
@@ -1,13 +1,29 @@
============================================================
- Generated by: Genus(TM) Synthesis Solution 17.10-p007_1
- Generated on: Sep 10 2019 10:42:40 am
+ Generated by: Genus(TM) Synthesis Solution 18.10-p003_1
+ Generated on: Oct 02 2019 02:33:05 pm
Module: compteur
- Technology library: fast_vdd1v0 1.0
- Operating conditions: PVT_1P1V_0C
+ Technology library: slow_vdd1v0 1.0
+ Operating conditions: PVT_0P9V_125C
Interconnect mode: global
Area mode: timing library
============================================================
+-------------------------------------------------------------------------------
+Timing exceptions with no effect
+
+The following timing exceptions are not currently affecting timing in the
+design. Either no paths in the design satisfy the exception's path
+specification, or all paths that satisfy the path specification also satisfy an
+exception with a higher priority. You can improve runtime and memory usage by
+removing these exceptions if they are not truly needed. To see if there is a
+path in the design that satisfies the path specification for an exception, or
+to see what other exception is overriding an exception because of priority, use
+the command:
+ report timing -paths [eval [::legacy::get_attribute paths <exception>]]
+
+exception:compteur/timing.sdc_line_28
+-------------------------------------------------------------------------------
+
Lint summary
Unconnected/logic driven clocks 0
@@ -20,7 +36,7 @@ Lint summary
Paths constrained with different clocks 0
Loop-breaking cells for combinational feedback 0
Nets with multiple drivers 0
- Timing exceptions with no effect 0
+ Timing exceptions with no effect 1
Suspicious multi_cycle exceptions 0
Pins/ports with conflicting case constants 0
Inputs without clocked external delays 0
@@ -29,4 +45,4 @@ Lint summary
Outputs without external load 0
Exceptions with invalid timing start-/endpoints 0
- Total: 0
+ Total: 1
diff --git a/compteur/scripts/pnr.tcl b/compteur/scripts/pnr.tcl
index 66b3198c51c7f2c4926e417ef7e30779c5556bd1..e094ac8327f85599054391cf7979a94f753c2704 100644
--- a/compteur/scripts/pnr.tcl
+++ b/compteur/scripts/pnr.tcl
@@ -1,14 +1,14 @@
#-----------------------------------------------------------------------------
-# Project : Tutoriels - Conception de circuits intégrés numériques
+# Project Tutoriels - Conception de circuits intégrés numériques
#-----------------------------------------------------------------------------
-# File : pnr.tcl
-# Authors : Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
-# Lab : GRM - Polytechnique Montréal
-# Date : <2019-07-24 Wed>
+# File pnr.tcl
+# Author Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
+# Lab GRM - Polytechnique Montreal
+# Date <2019-09-10 Tue>
#-----------------------------------------------------------------------------
-# Description: Placement et routage du compteur BCD avec Innovus
-# HOW-TO : source setup.csh && cd implementation/pnr && innovus
-# : innovus -files ${SCRIPTS_DIR}/pnr.tcl
+# Brief Placement & Routage du mini-mips avec Innovus
+# Usage cd implementation
+# innovus -files ../scripts/syn.tcl
#-----------------------------------------------------------------------------
package require Tcl 8.5
@@ -26,13 +26,14 @@ set DO_IO 1
set DO_PLACE 1
set DO_CTS 1
set DO_ROUTE 1
-set DO_CHECK 1
set DO_SAVE 1
set DESIGN compteur
-# Create directories if they do not exists
+# Répertoires de destination
file mkdir $::env(PNR_REP_DIR) $::env(PNR_NET_DIR)
+set OPT_DIR $::env(PNR_DIR)/opt
+set TIM_DIR $::env(PNR_DIR)/timing
#-----------------------------------------------------------------------------
# INIT
@@ -40,12 +41,12 @@ file mkdir $::env(PNR_REP_DIR) $::env(PNR_NET_DIR)
if { $DO_INIT } {
set init_oa_ref_lib [list gsclib045_tech gsclib045 giolib045]
- set init_mmmc_file $::env(CONST_DIR)/mmmc.tcl
set init_verilog $::env(SYN_NET_DIR)/${DESIGN}.syn.v
set init_design_settop 1
set init_top_cell $DESIGN
set init_gnd_net VSS
set init_pwr_net VDD
+ set init_mmmc_file $::env(CONST_DIR)/mmmc.tcl
init_design
}
@@ -94,7 +95,6 @@ if { $DO_POWER } {
#-----------------------------------------------------------------------------
if { $DO_IO } {
- # Nets
set top_nets [list [get_nets -quiet "i_clk"] \
[get_nets -quiet "i_rstn"] \
[get_nets -quiet "i_en"]]
@@ -125,11 +125,18 @@ if { $DO_IO } {
#-----------------------------------------------------------------------------
if { $DO_PLACE } {
- setDesignMode -process 45
+ # Timing
+ timeDesign -prePlace -outDir ${TIM_DIR}
+
+ # Placement
setPlaceMode -place_global_reorder_scan false
deleteAllScanCells
placeDesign
- report_timing > $::env(PNR_REP_DIR)/${DESIGN}.place.timing.rpt
+
+ # Netlist
+ saveNetlist $::env(PNR_NET_DIR)/${DESIGN}.place.v
+ write_sdf -version 2.1 -target_application verilog -interconn noport \
+ $::env(PNR_NET_DIR)/${DESIGN}.place.sdf
}
#-----------------------------------------------------------------------------
@@ -137,8 +144,6 @@ if { $DO_PLACE } {
#-----------------------------------------------------------------------------
if { $DO_CTS } {
- optDesign -preCTS -outDir $::env(PNR_REP_DIR)/cts
-
set_ccopt_property buffer_cells \
[list CLKBUFX20 CLKBUFX16 CLKBUFX12 CLKBUFX8 CLKBUFX6 CLKBUFX4 CLKBUFX3 CLKBUFX2]
@@ -147,10 +152,18 @@ if { $DO_CTS } {
set_ccopt_property use_inverters true
- ccopt_design -cts -outDir $::env(PNR_REP_DIR)/cts
- optDesign -postCTS -outDir $::env(PNR_REP_DIR)/cts
+ # Synthèse de l'arbre d'horloge
+ optDesign -preCTS -outDir ${OPT_DIR}
+ ccopt_design -cts -outDir ${OPT_DIR}
+ optDesign -postCTS -outDir ${OPT_DIR}
- report_timing > $::env(PNR_REP_DIR)/${DESIGN}.cts.timing.rpt
+ # Timing
+ timeDesign -postCTS -outDir ${TIM_DIR}
+
+ # Netlist
+ saveNetlist $::env(PNR_NET_DIR)/${DESIGN}.cts.v
+ write_sdf -version 2.1 -target_application verilog -interconn noport \
+ $::env(PNR_NET_DIR)/${DESIGN}.cts.sdf
}
#-----------------------------------------------------------------------------
@@ -158,29 +171,36 @@ if { $DO_CTS } {
#-----------------------------------------------------------------------------
if { $DO_ROUTE } {
- setNanoRouteMode -quiet -routeWithTimingDriven true
- routeDesign -globalDetail
-
+ # Ajout des filler cells
addFiller -cell FILL32 FILL16 FILL8 FILL4 FILL2 FILL1 -prefix FILLER
-}
-#-----------------------------------------------------------------------------
-# CHECK
-#-----------------------------------------------------------------------------
-if { $DO_CHECK } {
+ # Routage timing- et signal-integrity- driven
+ setNanoRouteMode -routeWithTimingDriven true
+ setNanoRouteMode -routeWithSIDriven true
+ routeDesign -GlobalDetail
- # DRC
+ # Extraction des capacités parasites
+ setExtractRCMode -engine postRoute
+ extractRC
+
+ # Optimisations post-route
+ setAnalysisMode -analysisType onChipVariation
+ setAnalysisMode -cppr both
+ optDesign -postRoute -setup -hold -outDir ${OPT_DIR}
+
+ # Verifications physiques
set_verify_drc_mode -report $::env(PNR_REP_DIR)/${DESIGN}.drc.rpt
verify_drc
-
- # Connectivity
verifyConnectivity -type all -error 1000 -warning 50 -report $::env(PNR_REP_DIR)/${DESIGN}.con.rpt
# Timing
- setAnalysisMode -analysisType onChipVariation
- reset_parasitics
- extractRC
+ timeDesign -postRoute -outDir ${TIM_DIR}
report_timing > $::env(PNR_REP_DIR)/${DESIGN}.timing.rpt
+
+ # Netlist
+ saveNetlist $::env(PNR_NET_DIR)/${DESIGN}.route.v
+ write_sdf -version 2.1 -target_application verilog -interconn noport \
+ $::env(PNR_NET_DIR)/${DESIGN}.route.sdf
}
#-----------------------------------------------------------------------------
@@ -191,13 +211,5 @@ if { $DO_SAVE } {
if {! [file isdirectory $::env(PNR_OA_LIB)] } {
createLib $::env(PNR_OA_LIB) -attachTech gsclib045_tech
}
-
saveDesign -cellview "$::env(PNR_OA_LIB) $DESIGN layout"
-
- saveNetlist $::env(PNR_NET_DIR)/${DESIGN}.pnr.v
- saveNetlist -phys $::env(PNR_NET_DIR)/${DESIGN}.pnr.phy.v
-
- write_sdf -view av_fast -target_application verilog -interconn noport \
- -recrem split -setuphold split -adjust_setuphold_for_zero_hold_slack \
- $::env(PNR_NET_DIR)/${DESIGN}.pnr.sdf
}
diff --git a/compteur/scripts/pwr.tcl b/compteur/scripts/pwr.tcl
index be82ae3097e797358935920829319cdb8d0b2079..4477e1fc4c44332d6638d3491c054625507fdd2d 100644
--- a/compteur/scripts/pwr.tcl
+++ b/compteur/scripts/pwr.tcl
@@ -1,14 +1,14 @@
#-----------------------------------------------------------------------------
-# Project : Tutoriels - Conception de circuits intégrés numériques
+# Project Tutoriels - Conception de circuits intégrés numériques
#-----------------------------------------------------------------------------
-# File : pwr.tcl
-# Authors : Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
-# Lab : GRM - Polytechnique Montréal
-# Date : <2019-07-24 Wed>
+# File pwr.tcl
+# Authors Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
+# Lab GRM - Polytechnique Montréal
+# Date <2019-10-02 Wed>
#-----------------------------------------------------------------------------
-# Description: Estimation du puissance du compteur BCD avec Voltus
-# HOW-TO : source setup.csh && cd implementation/pnr
-# : > voltus -files ${SCRIPTS_DIR}/pwr.tcl
+# Brief Estimation du puissance du compteur BCD avec Voltus
+# Usage source setup.csh && cd implementation/pnr
+# voltus -files ${SCRIPTS_DIR}/pwr.tcl
#-----------------------------------------------------------------------------
package require Tcl 8.5
@@ -20,24 +20,33 @@ if { ![info exist ::env(PROJECT_HOME)] } {
# CONFIG
#-----------------------------------------------------------------------------
set DO_INIT 1
-set DO_STAT 0
+set DO_STAT 1
set DO_DYN 1
set DESIGN compteur
+set DUT compteur_tb/dut
+set PERIOD 1250
set VCD_START 0
-set VCD_END 39
+set VCD_END 54375
#-----------------------------------------------------------------------------
# INIT
#-----------------------------------------------------------------------------
if { $DO_INIT } {
+ # Unités par défaut
+ set_time_unit -picoseconds
+
+ # Importation du layout
read_design -cellview "$::env(PNR_OA_LIB) $DESIGN layout" -physical_data
+ # Mise à jour du timing à partir du mmmc
+ set_analysis_view -update_timing
+
+ # Configuration
set_pg_library_mode -extraction_tech_file $::env(BE_QRC_LIB)/gpdk045.tch -celltype techonly \
- -default_area_cap 0.5 -power_pins {VDD 1.1} -ground_pins VSS \
+ -power_pins {VDD 1.1} -ground_pins VSS \
-decap_cells DECAP* -filler_cells FILL* \
- -current_distribution propagation
generate_pg_library -output $::env(PNR_REP_DIR)/power
}
@@ -49,19 +58,16 @@ if { $DO_STAT } {
set rep ${DESIGN}.stat
- # Static mode
+ # Configuration statique
set_power_analysis_mode -reset
set_power_analysis_mode -method static \
- -analysis_view av_fast \
-corner max \
-create_binary_db false \
- -write_static_currents false \
- -honor_negative_energy true \
- -ignore_control_signals true
+ -write_static_currents false
- # Activity
+ # Activité moyenne
set_default_switching_activity -reset
- set_default_switching_activity -input_activity 0.2 -period 1.0
+ set_default_switching_activity -input_activity 0.2 -period $PERIOD
}
#-----------------------------------------------------------------------------
@@ -71,25 +77,22 @@ if { $DO_DYN } {
set rep ${DESIGN}.dyn
- # Reset mode
+ # Configuration dynamique
set_power_analysis_mode -reset
- set_default_switching_activity -reset
-
- # Set dynamic mode
set_power_analysis_mode -method dynamic_vectorbased \
+ -enable_rtl_vectorbased_dynamic_analysis true \
-power_grid_library $::env(PNR_REP_DIR)/power/techonly.cl \
- -analysis_view av_fast -corner max \
+ -corner max \
-report_stat true \
- -enable_rtl_vectorbased_dynamic_analysis true \
-create_binary_db true \
- -disable_static false \
-write_static_currents true \
-report_missing_flop_outputs false
- # Read VCD activity file
+ # Activité issue du fichier VCD
+ set_default_switching_activity -reset
read_activity_file -reset
- read_activity_file -format VCD $::env(SIM_PNR_DIR)/${DESIGN}.pnr.vcd \
- -scope ${DESIGN}_tb/dut -start $VCD_START -end $VCD_END
+ read_activity_file -format VCD $::env(SIM_DIR)/pnr/${DESIGN}.vcd \
+ -scope $DUT -start $VCD_START -end $VCD_END
}
# Report power
diff --git a/compteur/scripts/sim.tcl b/compteur/scripts/sim.tcl
index c2abd9ef44a6117705cc1aec517040742368cc70..6b6de4d56c3e145c888d62d8e63771fda3ed51b3 100644
--- a/compteur/scripts/sim.tcl
+++ b/compteur/scripts/sim.tcl
@@ -20,19 +20,16 @@ if { ![info exist ::env(PROJECT_HOME)] } {
#-----------------------------------------------------------------------------
# CONFIG
#-----------------------------------------------------------------------------
-set DO_BEH 0; # Simulation du modèle comportemental
-set DO_SYN 0; # Smulation de la netlist post-synthèse
-set DO_PNR 1; # Simulation de la netlist post-implémentation
-set DO_RUN 1; # 0=Compilation; 1=Compilation + Simulation
-set DO_WAVE 0; # Chargement des chronogrammes
-set DO_VCD 1; # Enregistrement de l'activité dans un fichier vcd
+set DO_BEH 0; # Modèle comportemental
+set DO_SYN 0; # Netlist post-synthèse
+set DO_PNR 1; # Netlist post-placement-routage
+set DO_SIM 1; # 0=Compilation; 1=Compilation + Simulation
set top compteur
-set tb ${top}_tb
+set tb compteur_tb
set dut dut
set work work
set lib gpdk45
-set srcD $::env(PROJECT_HOME)/sources
if { $DO_BEH } { set workD $::env(SIM_DIR)/beh }
if { $DO_SYN } { set workD $::env(SIM_DIR)/syn }
@@ -43,53 +40,51 @@ set wlf ${workD}/${top}.wlf
set vcd ${workD}/${top}.vcd
set wave ${workD}/${top}.wave.do
-if { $DO_SYN } { set net $::env(SYN_NET_DIR)/${top}.syn }
-if { $DO_PNR } { set net $::env(PNR_NET_DIR)/${top}.pnr }
+if { $DO_SYN } { set net $::env(SYN_NET_DIR)/${top}.syn }
+if { $DO_PNR } { set net $::env(PNR_NET_DIR)/${top}.route }
#-----------------------------------------------------------------------------
-# COMPILATION & SIMULATION
+# COMPILATION
#-----------------------------------------------------------------------------
-# Create simulation directory if it does not exists
+# Création du répertoire de travail
if { ![file exist $workD] } {
file mkdir $workD
}
-# Copy the default modelsim.ini & Map the technology library
-if { ![file exist "./modelsim.ini"] } {
- vmap -c
- vmap $lib $::env(SIMLIB_VER)
+# Mise à jour du modelsim.ini avec les librairies GPDK45
+if { [file exist "./modelsim.ini"] } {
+ file delete "./modelsim.ini"
}
+vmap -c
+vmap $lib $::env(KIT_SIMLIB)/gsclib045_slow
-# Update Work Library
+# Work
if { [file exist ${workD}/${work}] } {
vdel -all -lib ${workD}/${work}
}
vlib ${workD}/${work}
vmap ${work} ${workD}/${work}
-# Behavioral
+# Model
if { $DO_BEH } {
+ vcom -2008 -work $work $::env(SRC_DIR)/${top}.vhd
+ vcom -2008 -work $work $::env(SRC_DIR)/${tb}.vhd
- vcom -2008 -work $work ${srcD}/${top}.vhd
- vcom -2008 -work $work ${srcD}/${tb}.vhd
- vsim -t ps -voptargs=+acc -logfile $log -wlf $wlf ${work}.${tb}
-
-# Timing
+# Netlist
} elseif { $DO_SYN || $DO_PNR } {
-
vlog -work $work ${net}.v
- vcom -2008 -work $work ${srcD}/${tb}.vhd
- vsim -t ps -voptargs=+acc -logfile $log -wlf $wlf -L $lib -sdfmax ${dut}=${net}.sdf ${work}.${tb}
+ vcom -2008 -work $work $::env(SRC_DIR)/${tb}.vhd
}
#-----------------------------------------------------------------------------
-# RUN
+# SIMULATION
#-----------------------------------------------------------------------------
-if { $DO_RUN } {
- if { $DO_WAVE } { do $wave }
- if { $DO_VCD } { vcd file $vcd; vcd add -r /${tb}/${dut}/* }
- run -all
- if { $DO_VCD } { vcd flush }
+if { $DO_SIM && $DO_BEH } {
+ vsim -c -t ps -voptargs=+acc -do run.do -logfile $log -wlf $wlf ${work}.${tb}
+}
+
+if { $DO_SIM && ($DO_SYN || $DO_PNR) } {
+ vsim -c -t ps -voptargs=+acc -do run.do -logfile $log -wlf $wlf -L $lib -sdfmax ${dut}=${net}.sdf ${work}.${tb}
}
diff --git a/compteur/scripts/syn.tcl b/compteur/scripts/syn.tcl
index 34a60684ef96d3343ed0b660b1cf83488f98e6d2..1989c5141b0c23550649d3f750080c7b9e04dad0 100644
--- a/compteur/scripts/syn.tcl
+++ b/compteur/scripts/syn.tcl
@@ -1,14 +1,14 @@
#-----------------------------------------------------------------------------
-# Project : Tutoriels - Conception de circuits intégrés numériques
+# Project Tutoriels - Conception de circuits intégrés numériques
#-----------------------------------------------------------------------------
-# File : syn.tcl
-# Authors : Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
-# Lab : GRM - Polytechnique Montréal
-# Date : <2019-07-24 Wed>
+# File syn.tcl
+# Author Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
+# Lab GRM - Polytechnique Montreal
+# Date <2019-10-01 Tue>
#-----------------------------------------------------------------------------
-# Description: Script pour la synthèse du compteur BCD avec Genus
-# HOW-TO : > source setup.csh && cd implementation/syn
-# : > genus -files ${SCRIPTS_DIR}/syn.tcl
+# Brief Synthèse du compteur avec Genus
+# Usage cd implementation
+# genus -files ../scripts/syn.tcl
#-----------------------------------------------------------------------------
package require Tcl 8.5
@@ -25,59 +25,80 @@ set DO_SDC 1
set DO_SYN 1
set DO_REPORTS 1
-set DESIGN compteur
-set SYN_EFFORT high; # low | medium | high | express
+set DESIGN compteur; # Top-level
+set SYN_EFFORT high; # low | medium | high | express
# Create directories if they do not exists
file mkdir $::env(SYN_REP_DIR) $::env(SYN_NET_DIR)
#-----------------------------------------------------------------------------
-# INIT
+# CONFIG
#-----------------------------------------------------------------------------
-if { $DO_INIT } {
+set DO_INIT 1
+set DO_ELAB 1
+set DO_SDC 1
+set DO_SYN 1
- # Paramètres de base
- set_db / .information_level 9; # Verbosité: 1-11
- set_db / .hdl_vhdl_read_version 2008; # Standard VHDL
- set_db / .max_cpus_per_server 4; # Numbre max de thread utilisable par genus
+set DESIGN compteur; # Top-level
+set SYN_EFFORT high; # low | medium | high | express
- # Sources
- set_db / .init_hdl_search_path [list $::env(SRC_DIR)]
+# Création des répertoires de destination
+file mkdir $::env(SYN_REP_DIR) $::env(SYN_NET_DIR)
- # Librairies: Timing + Standard Cells + Interconnect
- set_db / .init_lib_search_path [list $::env(FE_TIM_LIB) \
- $::env(BE_QRC_LIB) \
- $::env(BE_LEF_LIB) ]
+#-----------------------------------------------------------------------------
+# SAVE
+#-----------------------------------------------------------------------------
+proc save { basename } {
+ report_timing > $::env(SYN_REP_DIR)/${basename}.timing.rpt
+ report_area > $::env(SYN_REP_DIR)/${basename}.area.rpt
+ report_gates > $::env(SYN_REP_DIR)/${basename}.gates.rpt
+ report_power > $::env(SYN_REP_DIR)/${basename}.power.rpt
+}
- # Librairies "fast"
- read_libs "fast_vdd1v0_basicCells.lib"
- read_physical -lef "gsclib045_tech.lef"
- read_qrc "gpdk045.tch"
+#-----------------------------------------------------------------------------
+# INIT
+#-----------------------------------------------------------------------------
+if { $DO_INIT } {
- set_db / .interconnect_mode ple; # wireload ou ple (Physical Layout Estimators)
+ # Paramètres
+ set_db information_level 11; # Verbosité: 1-11
+ set_db max_cpus_per_server 8; # Numbre max de thread utilisable
+ set_db hdl_vhdl_read_version 2008; # Standard VHDL
+ set_db hdl_error_on_blackbox true; # Éviter les black-box
+ set_db hdl_error_on_latch true; # Éviter les latch
+
+ set_db init_hdl_search_path [list $::env(SRC_DIR)]
+ set_db init_lib_search_path [list $::env(FE_TIM_LIB) \
+ $::env(BE_LEF_LIB) \
+ $::env(BE_QRC_LIB)]
+
+ # Librairies de timing: max=setup, min=hold
+ read_libs -max_libs slow_vdd1v0_basicCells.lib -min_libs fast_vdd1v0_basicCells.lib
+
+ # Libraries physiques: stdcells + interconnect
+ read_physical -lef gsclib045_tech.lef
+ read_qrc gpdk045.tch
+ set_db interconnect_mode ple; # wireload | ple (Physical Layout Estimators)
}
#-----------------------------------------------------------------------------
# ELABORATION
#-----------------------------------------------------------------------------
-set sources [list compteur.vhd]
-
if { $DO_ELAB } {
- # Paramètres de compilation
- set_db / .hdl_error_on_blackbox true
- set_db / .hdl_error_on_latch true
-
# Compilation
- foreach src $sources {
- read_hdl -vhdl $src
- }
+ read_hdl -vhdl [list compteur.vhd]
+
+ # Conserver les compteurs de performance
+ set_db hdl_preserve_unused_flop true
# Élaboration
elaborate $DESIGN
- # Vérifications
- check_design -all
+ # Rapports
+ check_design -all > $::env(SYN_REP_DIR)/${DESIGN}.check.rpt
+ report_module -depth 3 > $::env(SYN_REP_DIR)/${DESIGN}.hier_elab.rpt
+ write_hdl > $::env(SYN_NET_DIR)/${DESIGN}.elab.v
}
#-----------------------------------------------------------------------------
@@ -88,44 +109,34 @@ if { $DO_SDC } {
# Contraintes de timing
read_sdc $::env(CONST_DIR)/timing.sdc
- # Vérification des contraintes de timing
- report_timing -lint > $::env(SYN_REP_DIR)/${DESIGN}.syn.timing_lint.rpt
+ # Rapports
+ report_timing -lint -verbose > $::env(SYN_REP_DIR)/${DESIGN}.timing_lint.rpt
+ report_clocks > $::env(SYN_REP_DIR)/${DESIGN}.clk.rpt
+ report_clocks -generated >> $::env(SYN_REP_DIR)/${DESIGN}.clk.rpt
}
#-----------------------------------------------------------------------------
-# SYNTHESE
+# SYNTHÈSE
#-----------------------------------------------------------------------------
if { $DO_SYN } {
- # Ungroup
- ungroup -all -simple
-
# Synthèse générique
- set_db / .syn_generic_effort ${SYN_EFFORT}
- syn_generic $DESIGN
+ set_db syn_generic_effort $SYN_EFFORT
+ syn_generic ${DESIGN}
+ save ${DESIGN}.gen
- # Mapping des cellules standards
- set_db / .syn_map_effort ${SYN_EFFORT}
- syn_map $DESIGN
+ # Map
+ set_db syn_map_effort $SYN_EFFORT
+ syn_map ${DESIGN}
+ save ${DESIGN}.map
# Optimisations
- set_db / .syn_opt_effort ${SYN_EFFORT}
- syn_opt $DESIGN
-}
-
-#-----------------------------------------------------------------------------
-# RAPPORTS & NETLIST
-#-----------------------------------------------------------------------------
-if { $DO_REPORTS } {
-
- # Rapports
- report_timing > $::env(SYN_REP_DIR)/${DESIGN}.syn.timing.rpt
- report_area > $::env(SYN_REP_DIR)/${DESIGN}.syn.area.rpt
- report_gates > $::env(SYN_REP_DIR)/${DESIGN}.syn.gates.rpt
- report_power > $::env(SYN_REP_DIR)/${DESIGN}.syn.power.rpt
+ set_db syn_opt_effort $SYN_EFFORT
+ syn_opt ${DESIGN}
+ save ${DESIGN}.syn
# Netlist
- write_hdl > $::env(SYN_NET_DIR)/${DESIGN}.syn.v
- write_sdf > $::env(SYN_NET_DIR)/${DESIGN}.syn.sdf
write_sdc > $::env(CONST_DIR)/${DESIGN}.syn.sdc
+ write_hdl > $::env(SYN_NET_DIR)/${DESIGN}.syn.v
+ write_sdf -nonegchecks -setuphold split -version 2.1 > $::env(SYN_NET_DIR)/${DESIGN}.syn.sdf
}
diff --git a/compteur/setup.csh b/compteur/setup.csh
index 56fd162d0261c4e964a399604d2881a6d25463e9..141eacc2477b20faecfbb154d44956e4547f0a80 100644
--- a/compteur/setup.csh
+++ b/compteur/setup.csh
@@ -2,16 +2,16 @@
#-----------------------------------------------------------------------------
# Project : Tutoriels - Conception de circuits intégrés numériques
#-----------------------------------------------------------------------------
-# File : setup.csh
-# Authors : Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
-# Lab : GRM - Polytechnique Montréal
-# Date : <2019-07-24 Wed>
+# File setup.csh
+# Authors Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
+# Lab GRM - Polytechnique Montréal
+# Date <2019-10-01 Tue>
#-----------------------------------------------------------------------------
-# Description: Script de configuration de l'environnement
-# + Environnement CMC
-# + Hiérarchie du projet
-# + kit GPDK045
-# + Outils Cadence & Mentor
+# Brief Script de configuration de l'environnement
+# - Environnement CMC
+# - Hiérarchie du projet
+# - kit GPDK45
+# - Outils Cadence & Mentor
#-----------------------------------------------------------------------------
#-----------------------------------------------------------------------------
@@ -39,10 +39,9 @@ source ${CMC_CONFIG}
#-----------------------------------------------------------------------------
setenv SRC_DIR ${PROJECT_HOME}/sources
setenv CONST_DIR ${PROJECT_HOME}/constraints
+setenv SCRIPTS_DIR ${PROJECT_HOME}/scripts
setenv SIM_DIR ${PROJECT_HOME}/simulation
setenv IMP_DIR ${PROJECT_HOME}/implementation
-setenv DOC_DIR ${PROJECT_HOME}/../doc
-setenv SCRIPTS_DIR ${PROJECT_HOME}/scripts
setenv SYN_DIR ${IMP_DIR}/syn
setenv SYN_NET_DIR ${SYN_DIR}/netlist
setenv SYN_REP_DIR ${SYN_DIR}/reports
@@ -55,15 +54,11 @@ setenv PNR_OA_LIB liboa
#-----------------------------------------------------------------------------
# CONFIGURATION DU KIT GPDK045
#-----------------------------------------------------------------------------
-setenv KIT_HOME ${CMC_HOME}/kits/GPDK45
-setenv KIT_SCLIB ${KIT_HOME}/gsclib045
-setenv KIT_IOLIB ${KIT_HOME}/giolib045
-setenv KIT_GPDK ${KIT_HOME}/gpdk045
-
-# Simulations
-setenv SIMLIB ${KIT_HOME}/simlib
-setenv SIMLIB_VHD ${SIMLIB}/gsclib045_vital
-setenv SIMLIB_VER ${SIMLIB}/gsclib045_verilog
+setenv KIT_HOME ${CMC_HOME}/kits/GPDK45
+setenv KIT_SCLIB ${KIT_HOME}/gsclib045
+setenv KIT_IOLIB ${KIT_HOME}/giolib045
+setenv KIT_GPDK ${KIT_HOME}/gpdk045
+setenv KIT_SIMLIB ${KIT_HOME}/simlib
# Front-End
setenv FE_DIR ${KIT_SCLIB}/gsclib045
@@ -91,9 +86,6 @@ setenv IO_OA_LIB ${IO_DIR}/oa22/giolib045
# CONFIGURATION DES OUTILS
#-----------------------------------------------------------------------------
-# MENTOR
-source ${CMC_HOME}/scripts/mentor.2017.12.csh
-
# MODELSIM
source ${CMC_HOME}/scripts/mentor.modelsim.10.7c.csh
alias vsim "vsim -64"
@@ -107,27 +99,26 @@ endif
setenv DRCTEMPDIR /export/tmp/$user
# GENUS
-source ${CMC_HOME}/scripts/cadence.genus17.10.000.csh
+source ${CMC_HOME}/scripts/cadence.genus18.10.000.csh
alias genus "genus -overwrite"
-alias genus_help "${CMC_CDS_GENUS_HOME}/tools/bin/cdnshelp"
+alias genus_help "${CMC_CDS_GENUS_HOME}/bin/cdnshelp"
# INNOVUS
-source ${CMC_HOME}/scripts/cadence.innovus17.11.000.csh
+source ${CMC_HOME}/scripts/cadence.innovus18.10.000.csh
alias innovus "innovus -overwrite -no_logv"
-alias innovus_help "${CMC_CDS_INNOVUS_HOME}/tools/bin/cdnshelp"
+alias innovus_help "${CMC_CDS_INNOVUS_HOME}/bin/cdnshelp"
# VOLTUS & TEMPUS
source ${CMC_HOME}/scripts/cadence.ssv16.16.000.csh
alias voltus "voltus -overwrite -no_logv"
alias tempus "tempus -overwrite -no_logv"
-alias voltus_help "${CMC_CDS_SSV_HOME}/bin/cdnshelp"
-alias tempus_help "${CMC_CDS_SSV_HOME}/bin/cdnshelp"
+alias ssv_help "${CMC_CDS_SSV_HOME}/bin/cdnshelp"
# QUANTUS QRC
-source ${CMC_HOME}/scripts/cadence.ext17.21.000.csh
+source ${CMC_HOME}/scripts/cadence.ext19.10.000.csh
# CONFORMAL
-source ${CMC_HOME}/scripts/cadence.conformal17.20.300.csh
+source ${CMC_HOME}/scripts/cadence.conformal18.10.100.csh
# PVS
-source ${CMC_HOME}/scripts/cadence.pvs16.12.000.csh
+source ${CMC_HOME}/scripts/cadence.pvs16.15.000.csh
diff --git a/compteur/simulation/beh/compteur.wave.do b/compteur/simulation/beh/compteur.wave.do
deleted file mode 100644
index 694d8cdab6690d4d1a78026e75506c5b9dbbe8c8..0000000000000000000000000000000000000000
--- a/compteur/simulation/beh/compteur.wave.do
+++ /dev/null
@@ -1,25 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate /compteur_tb/clk
-add wave -noupdate /compteur_tb/rst_n
-add wave -noupdate /compteur_tb/dut/rstn
-add wave -noupdate /compteur_tb/en
-add wave -noupdate /compteur_tb/cnt
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {3611 ps} 0}
-quietly wave cursor active 1
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 0
-configure wave -timelineunits ns
-update
-WaveRestoreZoom {0 ps} {40530 ps}
diff --git a/compteur/simulation/modelsim.ini b/compteur/simulation/modelsim.ini
new file mode 100644
index 0000000000000000000000000000000000000000..2583d9ed0064220e6f0ccb8c00e04d10db11bca4
--- /dev/null
+++ b/compteur/simulation/modelsim.ini
@@ -0,0 +1,2127 @@
+; vsim modelsim.ini file
+[Version]
+INIVersion = "10.7c"
+
+; Copyright 1991-2018 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;
+
+[Library]
+others = $MODEL_TECH/../modelsim.ini
+;
+; VITAL concerns:
+;
+; The library ieee contains (among other packages) the packages of the
+; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use
+; the physical library ieee (recommended), or use the physical library
+; vital2000, but not both. The design can use logical library ieee and/or
+; vital2000 as long as each of these maps to the same physical library, either
+; ieee or vital2000.
+;
+; A design using the 1995 version of the VITAL packages, whether or not
+; it also uses the 2000 version of the VITAL packages, must have logical library
+; name ieee mapped to physical library vital1995. (A design cannot use library
+; vital1995 directly because some packages in this library use logical name ieee
+; when referring to the other packages in the library.) The design source
+; should use logical name ieee when referring to any packages there except the
+; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical
+; name vital2000 (mapped to physical library vital2000) to refer to those
+; packages.
+; ieee = $MODEL_TECH/../vital1995
+;
+; For compatiblity with previous releases, logical library name vital2000 maps
+; to library vital2000 (a different library than library ieee, containing the
+; same packages).
+; A design should not reference VITAL from both the ieee library and the
+; vital2000 library because the vital packages are effectively different.
+; A design that references both the ieee and vital2000 libraries must have
+; both logical names ieee and vital2000 mapped to the same library, either of
+; these:
+; $MODEL_TECH/../ieee
+; $MODEL_TECH/../vital2000
+;
+
+; added mapping for ADMS
+
+;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release
+;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
+;mvc_lib = $MODEL_TECH/../mvc_lib
+
+; Automatically perform logical->physical mapping for physical libraries that
+; appear in -L/-Lf options with filesystem path delimiters (e.g. '.' or '/').
+; The tail of the filesystem path name is chosen as the logical library name.
+; For example, in the command "vopt -L ./path/to/lib1 -o opttop top",
+; vopt automatically performs the mapping "lib1 -> ./path/to/lib1".
+; See the User Manual for more details.
+;
+; AutoLibMapping = 0
+
+gpdk45 = /CMC/kits/GPDK45/simlib/gsclib045_slow
+work = /export/tmp/fiorentino/Projects/tutoriel_numerique/compteur/simulation/pnr/work
+[DefineOptionset]
+; Define optionset entries for the various compilers, vmake, and vsim.
+; These option sets can be used with the "-optionset <optionsetname>" syntax.
+; i.e.
+; vlog -optionset COMPILEDEBUG top.sv
+; vsim -optionset UVMDEBUG my_top
+;
+; Following are some useful examples.
+
+; define a vsim optionset for uvm debugging
+UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop
+
+; define a vopt optionset for debugging
+VOPTDEBUG = +acc -debugdb
+
+[encryption]
+; For vencrypt and vhencrypt.
+
+; Controls whether to encrypt whole files by ignoring all protect directives
+; (except "viewport" and "interface_viewport") that are present in the input.
+; The default is 0, use embedded protect directives to control the encryption.
+; Set this to 1 to encrypt whole files by ignoring embedded protect directives.
+; wholefile = 0
+
+; Sets the data_method to use for the symmetric session key.
+; The session key is a symmetric key that is randomly generated for each
+; protected region (envelope) and is the heart of all encryption. This is used
+; to set the length of the session key to generate and use when encrypting the
+; HDL text. Supported values are aes128, aes192, and aes256.
+; data_method = aes128
+
+; The following 2 are for specifying an IEEE Std. 1735 Version 2 (V2) encryption
+; "recipe" comprising an optional common block, at least one tool block (which
+; contains the key public key), and the text to be encrypted. The common block
+; and any of the tool blocks may contain rights in the form of the "control"
+; directive. The text to be encrypted is specified either by setting
+; "wholefile" to 1 or by embedding protect "begin" and "end" directives in
+; the input HDL files.
+
+; Common recipe specification file. This file is optional. Its presence will
+; require at least one "toolblock" to be specified.
+; Directives such as "author" "author_info" and "data_method",
+; as well as the common block license specification, go in this file.
+; common = <file name>
+
+; Tool block specification recipe(s). Public key file with optional tool block
+; file name. May be multiply-defined; at least one tool block is required if
+; a recipe is being specified.
+; Key file is a file name with no extension (.deprecated or .active will be
+; supplied by the encryption tool).
+; Rights file name is optional.
+; toolblock = <key file name>[,<rights file name>]{:<key file name>[,<rights file name>]}
+
+; Location of directory containing recipe files.
+; The default location is in the product installation directory.
+; keyring = $MODEL_TECH/../keyring
+
+; Enable encryption statistics. Specify one or more arguments:
+; [all,none,time,cmd,msg,perf,verbose,list]
+; Add '-' to disable specific statistics. Default is [cmd,msg].
+Stats = cmd,msg
+
+[vcom]
+; VHDL93 variable selects language version as the default.
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Value of 3 or 2008 for VHDL-2008
+; Value of 4 or ams99 for VHDL-AMS-1999
+; Value of 5 or ams07 for VHDL-AMS-2007
+VHDL93 = 2002
+
+; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off.
+; ignoreStandardRealVector = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Enable compiler statistics. Specify one or more arguments:
+; [all,none,time,cmd,msg,perf,verbose,list]
+; Add '-' to disable specific statistics. Default is [time,cmd,msg].
+; Stats = time,cmd,msg
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Turn off PSL assertion warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Treat as errors:
+; case statement static warnings
+; warnings caused by aggregates that are not locally static
+; Overrides NoCaseStaticError, NoOthersStaticError settings.
+; PedanticErrors = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+; -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Perform default binding at compile time.
+; Default is to do default binding at load time.
+; BindAtCompile = 1;
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+; Set the prefix to be honored for synthesis/coverage pragma recognition.
+; Default is "".
+; AddPragmaPrefix = ""
+
+; Ignore synthesis and coverage pragmas with this prefix.
+; Default is "".
+; IgnorePragmaPrefix = ""
+
+; Turn on code coverage in VHDL design units. Default is off.
+; Coverage = sbceft
+
+; Turn off code coverage in VHDL subprograms. Default is on.
+; CoverSub = 0
+
+; Automatically exclude VHDL case statement OTHERS choice branches.
+; This includes OTHERS choices in selected signal assigment statements.
+; Default is to not exclude.
+; CoverExcludeDefault = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Turn on or off clkOpt optimization for code coverage. Default is on.
+; CoverClkOpt = 1
+
+; Turn on or off clkOpt optimization builtins for code coverage. Default is on.
+; CoverClkOptBuiltins = 0
+
+; Inform code coverage optimizations to respect VHDL 'H' and 'L'
+; values on signals in conditions and expressions, and to not automatically
+; convert them to '1' and '0'. Default is to not convert.
+; CoverRespectHandL = 0
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a VHDL condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Increase or decrease the limit on the size of expressions and conditions
+; considered for expression and condition coverages. Higher FecUdpEffort leads
+; to higher compile, optimize and simulation time, but more expressions and
+; conditions are considered for coverage in the design. FecUdpEffort can
+; be set to a number ranging from 1 (low) to 3 (high), defined as:
+; 1 - (low) Only small expressions and conditions considered for coverage.
+; 2 - (medium) Bigger expressions and conditions considered for coverage.
+; 3 - (high) Very large expressions and conditions considered for coverage.
+; The default setting is 1 (low).
+; FecUdpEffort = 1
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable UDP Coverage analysis for conditions and expressions.
+; UDP Coverage data is disabled by default when expression and/or condition
+; coverage is active.
+; CoverUDP = 1
+
+; Enable or disable Rapid Expression Coverage mode for conditions and expressions.
+; Disabling this would convert non-masking conditions in FEC tables to matching
+; input patterns.
+; CoverREC = 1
+
+; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions
+; for expression/condition coverage.
+; NOTE: Enabling this may have a negative impact on simulation performance.
+; CoverExpandReductionPrefix = 0
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Enable deglitching of code coverage in combinatorial, non-clocked, processes.
+; Default is no deglitching.
+; CoverDeglitchOn = 1
+
+; Control the code coverage deglitching period. A period of 0, eliminates delta
+; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a
+; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps".
+; CoverDeglitchPeriod = 0
+
+; Use this directory for compiler temporary files instead of "work/_temp"
+; CompilerTempDir = /tmp
+
+; Set this to cause the compilers to force data to be committed to disk
+; when the files are closed.
+; SyncCompilerFiles = 1
+
+; Add VHDL-AMS declarations to package STANDARD
+; Default is not to add
+; AmsStandard = 1
+
+; Range and length checking will be performed on array indices and discrete
+; ranges, and when violations are found within subprograms, errors will be
+; reported. Default is to issue warnings for violations, because subprograms
+; may not be invoked.
+; NoDeferSubpgmCheck = 0
+
+; Turn ON detection of FSMs having single bit current state variable.
+; FsmSingle = 1
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Turn ON detection of FSM Implicit Transitions.
+; FsmImplicitTrans = 1
+
+; Controls whether or not to show immediate assertions with constant expressions
+; in GUI/report/UCDB etc. By default, immediate assertions with constant
+; expressions are shown in GUI/report/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Controls how VHDL basic identifiers are stored with the design unit.
+; Does not make the language case-sensitive, affects only how declarations
+; declared with basic identifiers have their names stored and printed
+; (in the GUI, examine, etc.).
+; Default is to preserve the case as originally depicted in the VHDL source.
+; Value of 0 indicates to change all basic identifiers to lower case.
+; PreserveCase = 0
+
+; For Configuration Declarations, controls the effect that USE clauses have
+; on visibility inside the configuration items being configured. If 1
+; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance,
+; extend the visibility of objects made visible through USE clauses into nested
+; component configurations.
+; OldVHDLConfigurationVisibility = 0
+
+; Allows VHDL configuration declarations to be in a different library from
+; the corresponding configured entity. Default is to not allow this for
+; stricter LRM-compliance.
+; SeparateConfigLibrary = 1;
+
+; Determine how mode OUT subprogram parameters of type array and record are treated.
+; If 0 (the default), then only VHDL 2008 will do this initialization.
+; If 1, always initialize the mode OUT parameter to its default value.
+; If 2, do not initialize the mode OUT out parameter.
+; Note that prior to release 10.1, all language versions did not initialize mode
+; OUT array and record type parameters, unless overridden here via this mechanism.
+; In release 10.1 and later, only files compiled with VHDL 2008 will cause this
+; initialization, unless overridden here.
+; InitOutCompositeParam = 0
+
+; Generate symbols debugging database in only some special cases to save on
+; the number of files in the library. For other design-units, this database is
+; generated on-demand in vsim.
+; Default is to to generate debugging database for all design-units.
+; SmartDbgSym = 1
+
+; Enable or disable automatic creation of missing libraries.
+; Default is 1 (enabled)
+; CreateLib = 1
+
+[vlog]
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn on `protect compiler directive processing.
+; Default is to ignore `protect directives.
+; Protect = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn on bad option warning. Default is off.
+; Show_BadOptionWarning = 1
+
+; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
+; vlog95compat = 1
+
+; Turn off PSL warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Enable compiler statistics. Specify one or more arguments:
+; [all,none,time,cmd,msg,perf,verbose,list,kb]
+; Add '-' to disable specific statistics. Default is [time,cmd,msg].
+; Stats = time,cmd,msg
+
+; Set the threshold for automatically identifying sparse Verilog memories.
+; A memory with total size in bytes equal to or more than the sparse memory
+; threshold gets marked as sparse automatically, unless specified otherwise
+; in source code or by the +nosparse commandline option of vlog or vopt.
+; The default is 1M. (i.e. memories with total size equal
+; to or greater than 1Mb are marked as sparse)
+; SparseMemThreshold = 1048576
+
+; Set the prefix to be honored for synthesis and coverage pragma recognition.
+; Default is "".
+; AddPragmaPrefix = ""
+
+; Ignore synthesis and coverage pragmas with this prefix.
+; Default is "".
+; IgnorePragmaPrefix = ""
+
+; Set the option to treat all files specified in a vlog invocation as a
+; single compilation unit. The default value is set to 0 which will treat
+; each file as a separate compilation unit as specified in the P1800 draft standard.
+; MultiFileCompilationUnit = 1
+
+; Turn on code coverage in Verilog design units. Default is off.
+; Coverage = sbceft
+
+; Automatically exclude Verilog case statement default branches.
+; Default is to not automatically exclude defaults.
+; CoverExcludeDefault = 1
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a VHDL condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Increase or decrease the limit on the size of expressions and conditions
+; considered for expression and condition coverages. Higher FecUdpEffort leads
+; to higher compile, optimize and simulation time, but more expressions and
+; conditions are considered for coverage in the design. FecUdpEffort can
+; be set to a number ranging from 1 (low) to 3 (high), defined as:
+; 1 - (low) Only small expressions and conditions considered for coverage.
+; 2 - (medium) Bigger expressions and conditions considered for coverage.
+; 3 - (high) Very large expressions and conditions considered for coverage.
+; The default setting is 1 (low).
+; FecUdpEffort = 1
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable UDP Coverage analysis for conditions and expressions.
+; UDP Coverage data is disabled by default when expression and/or condition
+; coverage is active.
+; CoverUDP = 1
+
+; Enable or disable Rapid Expression Coverage mode for conditions and expressions.
+; Disabling this would convert non-masking conditions in FEC tables to matching
+; input patterns.
+; CoverREC = 1
+
+; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions
+; for expression/condition coverage.
+; NOTE: Enabling this may have a negative impact on simulation performance.
+; CoverExpandReductionPrefix = 0
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+; Enable deglitching of code coverage in combinatorial, non-clocked, processes.
+; Default is no deglitching.
+; CoverDeglitchOn = 1
+
+; Control the code coverage deglitching period. A period of 0, eliminates delta
+; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a
+; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps".
+; CoverDeglitchPeriod = 0
+
+; Turn on code coverage in VLOG `celldefine modules, modules containing
+; specify blocks, and modules included using vlog -v and -y. Default is off.
+; CoverCells = 1
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. This is a number from 0 to 5, with the following
+; meanings (the default is 3):
+; 5 -- All allowable optimizations are on.
+; 4 -- Turn off removing unreferenced code.
+; 3 -- Turn off process, always block and if statement merging.
+; 2 -- Turn off expression optimization, converting primitives
+; to continuous assignments, VHDL subprogram inlining.
+; and VHDL clkOpt (converting FF's to builtins).
+; 1 -- Turn off continuous assignment optimizations and clock suppression.
+; 0 -- Turn off Verilog module inlining and VHDL arch inlining.
+; HOWEVER, if fsm coverage is turned on, optimizations will be forced to
+; level 3, with also turning off converting primitives to continuous assigns.
+; CoverOpt = 3
+
+; Specify the override for the default value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then LRM default
+; value of 0 (zero) is used. This is a compile time option.
+; SVCrossNumPrintMissingDefault = 0
+
+; Setting following to 1 would cause creation of variables which
+; would represent the value of Coverpoint expressions. This is used
+; in conjunction with "SVCoverpointExprVariablePrefix" option
+; in the modelsim.ini
+; EnableSVCoverpointExprVariable = 0
+
+; Specify the override for the prefix used in forming the variable names
+; which represent the Coverpoint expressions. This is used in conjunction with
+; "EnableSVCoverpointExprVariable" option of the modelsim.ini
+; The default prefix is "expr".
+; The variable name is
+; variable name => <prefix>_<coverpoint name>
+; SVCoverpointExprVariablePrefix = expr
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross option.goal (defined to be 100 in the LRM).
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupGoalDefault = 100
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupTypeGoalDefault = 100
+
+; Specify the override for the default value of "strobe" option for the
+; Covergroup Type. This is a compile time option which forces "strobe" to
+; a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero). NOTE: This can be overriden by a runtime
+; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section.
+; SVCovergroupStrobeDefault = 0
+
+; Specify the override for the default value of "per_instance" option for the
+; Covergroup variables. This is a compile time option which forces "per_instance"
+; to a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero).
+; SVCovergroupPerInstanceDefault = 0
+
+; Specify the override for the default value of "get_inst_coverage" option for the
+; Covergroup variables. This is a compile time option which forces
+; "get_inst_coverage" to a user specified default value and supersedes
+; SystemVerilog specified default value of '0'(zero).
+; SVCovergroupGetInstCoverageDefault = 0
+
+;
+; A space separated list of resource libraries that contain precompiled
+; packages. The behavior is identical to using the "-L" switch.
+;
+; LibrarySearchPath = <path/lib> [<path/lib> ...]
+LibrarySearchPath = mtiAvm mtiRnm mtiOvm mtiUvm mtiUPF infact
+
+; The behavior is identical to the "-mixedansiports" switch. Default is off.
+; MixedAnsiPorts = 1
+
+; Enable SystemVerilog 3.1a $typeof() function. Default is off.
+; EnableTypeOf = 1
+
+; Only allow lower case pragmas. Default is disabled.
+; AcceptLowerCasePragmaOnly = 1
+
+; Set the maximum depth permitted for a recursive include file nesting.
+; IncludeRecursionDepthMax = 5
+
+; Turn ON detection of FSMs having single bit current state variable.
+; FsmSingle = 1
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Turn off detections of FSMs having x-assignment.
+; FsmXAssign = 0
+
+; Turn ON detection of FSM Implicit Transitions.
+; FsmImplicitTrans = 1
+
+; List of file suffixes which will be read as SystemVerilog. White space
+; in extensions can be specified with a back-slash: "\ ". Back-slashes
+; can be specified with two consecutive back-slashes: "\\";
+; SvFileSuffixes = sv svp svh
+
+; This setting is the same as the vlog -sv command line switch.
+; Enables SystemVerilog features and keywords when true (1).
+; When false (0), the rules of IEEE Std 1364-2001 are followed and
+; SystemVerilog keywords are ignored.
+; Svlog = 0
+
+; Prints attribute placed upon SV packages during package import
+; when true (1). The attribute will be ignored when this
+; entry is false (0). The attribute name is "package_load_message".
+; The value of this attribute is a string literal.
+; Default is true (1).
+; PrintSVPackageLoadingAttribute = 1
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Controls if untyped parameters that are initialized with values greater
+; than 2147483647 are mapped to generics of type INTEGER or ignored.
+; If mapped to VHDL Integers, values greater than 2147483647
+; are mapped to negative values.
+; Default is to map these parameter to generic of type INTEGER
+; ForceUnsignedToVHDLInteger = 1
+
+; Enable AMS wreal (wired real) extensions. Default is 0.
+; WrealType = 1
+
+; Controls SystemVerilog Language Extensions. These options enable
+; some non-LRM compliant behavior.
+; SvExtensions = [+|-]<extension>[,[+|-]<extension>*]
+
+; Generate symbols debugging database in only some special cases to save on
+; the number of files in the library. For other design-units, this database is
+; generated on-demand in vsim.
+; Default is to to generate debugging database for all design-units.
+; SmartDbgSym = 1
+
+; Controls how $unit library entries are named. Valid options are:
+; "file" (generate name based on the first file on the command line)
+; "du" (generate name based on first design unit following an item
+; found in $unit scope)
+; CUAutoName = file
+
+; Enable or disable automatic creation of missing libraries.
+; Default is 1 (enabled)
+; CreateLib = 1
+
+[sccom]
+; Enable use of SCV include files and library. Default is off.
+; UseScv = 1
+
+; Add C++ compiler options to the sccom command line by using this variable.
+; CppOptions = -g
+
+; Use custom C++ compiler located at this path rather than the default path.
+; The path should point directly at a compiler executable.
+; CppPath = /usr/bin/g++
+
+; Specify the compiler version from the list of support GNU compilers.
+; examples 4.3.3, 4.5.0
+; CppInstall = 4.5.0
+
+; Enable verbose messages from sccom. Default is off.
+; SccomVerbose = 1
+
+; sccom logfile. Default is no logfile.
+; SccomLogfile = sccom.log
+
+; Enable use of SC_MS include files and library. Default is off.
+; UseScMs = 1
+
+; Use SystemC-2.2 instead of the default SystemC-2.3. Default is off.
+; Sc22Mode = 1
+
+; Enable compiler statistics. Specify one or more arguments:
+; [all,none,time,cmd,msg,perf,verbose,list,kb]
+; Add '-' to disable specific statistics. Default is [time,cmd,msg].
+; Stats = time,cmd,msg
+
+; Enable or disable automatic creation of missing libraries.
+; Default is 1 (enabled)
+; CreateLib = 1
+
+; Enable use of UVMC library. Default is off.
+; UseUvmc = 1
+
+[vopt]
+; Turn on code coverage in vopt. Default is off.
+; Coverage = sbceft
+
+; Control compiler optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Controls set of CoverConstructs that are being considered for Coverage
+; Collection.
+; Some of Valid options are: default,set1,set2
+; Covermode = default
+
+; Controls set of HDL cover constructs that would be considered(or not considered)
+; for Coverage Collection. (Default corresponds to covermode default).
+; Some of Valid options are: "ca", "citf", "cifl", "tcint", "fsmqs".
+; Coverconstruct = noca,nocitf,nofsmtf,nofsmds,noctes,nocicl,nocprc,nocfl,nofsmup,nocifl,nocpm,notcint,nocpkg,nocsva
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a VHDL condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Increase or decrease the limit on the size of expressions and conditions
+; considered for expression and condition coverages. Higher FecUdpEffort leads
+; to higher compile, optimize and simulation time, but more expressions and
+; conditions are considered for coverage in the design. FecUdpEffort can
+; be set to a number ranging from 1 (low) to 3 (high), defined as:
+; 1 - (low) Only small expressions and conditions considered for coverage.
+; 2 - (medium) Bigger expressions and conditions considered for coverage.
+; 3 - (high) Very large expressions and conditions considered for coverage.
+; The default setting is 1 (low).
+; FecUdpEffort = 1
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Enable deglitching of code coverage in combinatorial, non-clocked, processes.
+; Default is no deglitching.
+; CoverDeglitchOn = 1
+
+; Enable compiler statistics. Specify one or more arguments:
+; [all,none,time,cmd,msg,perf,verbose,list,kb]
+; Add '-' to disable specific statistics. Default is [time,cmd,msg].
+; Stats = time,cmd,msg
+
+; Control the code coverage deglitching period. A period of 0, eliminates delta
+; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a
+; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps".
+; CoverDeglitchPeriod = 0
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Set the maximum number of iterations permitted for a generate loop.
+; Restricting this permits the implementation to recognize infinite
+; generate loops.
+; GenerateLoopIterationMax = 100000
+
+; Set the maximum depth permitted for a recursive generate instantiation.
+; Restricting this permits the implementation to recognize infinite
+; recursions.
+; GenerateRecursionDepthMax = 200
+
+; Set the number of processes created during the code generation phase.
+; By default a heuristic is used to set this value. This may be set to 0
+; to disable this feature completely.
+; ParallelJobs = 0
+
+; Controls SystemVerilog Language Extensions. These options enable
+; some non-LRM compliant behavior.
+; SvExtensions = [+|-]<extension>[,[+|-]<extension>*]
+
+; Load the specified shared objects with the RTLD_GLOBAL flag.
+; This gives global visibility to all symbols in the shared objects,
+; meaning that subsequently loaded shared objects can bind to symbols
+; in the global shared objects. The list of shared objects should
+; be whitespace delimited. This option is not supported on the
+; Windows or AIX platforms.
+; GlobalSharedObjectList = example1.so example2.so example3.so
+
+; Disable SystemVerilog elaboration system task messages
+; IgnoreSVAInfo = 1
+; IgnoreSVAWarning = 1
+; IgnoreSVAError = 1
+; IgnoreSVAFatal = 1
+
+; Enable or disable automatic creation of missing libraries.
+; Default is 1 (enabled)
+; CreateLib = 1
+
+[vsim]
+; vopt flow
+; Set to turn on automatic optimization of a design.
+; Default is on
+VoptFlow = 1
+
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ns
+
+; Disable certain code coverage exclusions automatically.
+; Assertions and FSM are exluded from the code coverage by default
+; Set AutoExclusionsDisable = fsm to enable code coverage for fsm
+; Set AutoExclusionsDisable = assertions to enable code coverage for assertions
+; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions
+; Or specify comma or space separated list
+;AutoExclusionsDisable = fsm,assertions
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 10000000
+
+; Specify libraries to be searched for precompiled modules
+; LibrarySearchPath = <path/lib> [<path/lib> ...]
+
+; Set XPROP assertion fail limit. Default is 5.
+; Any positive integer, -1 for infinity.
+; XpropAssertionLimit = 5
+
+; Control PSL and Verilog Assume directives during simulation
+; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
+; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
+; SimulateAssumeDirectives = 1
+
+; Control the simulation of PSL and SVA
+; These switches can be overridden by the vsim command line switches:
+; -psl, -nopsl, -sva, -nosva.
+; Set SimulatePSL = 0 to disable PSL simulation
+; Set SimulatePSL = 1 to enable PSL simulation (default)
+; SimulatePSL = 1
+; Set SimulateSVA = 0 to disable SVA simulation
+; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
+; SimulateSVA = 1
+
+; Control SVA and VHDL immediate assertion directives during simulation
+; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts
+; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts
+; SimulateImmedAsserts = 1
+
+; License feature mappings for Verilog and VHDL
+; qhsimvh Single language VHDL license
+; qhsimvl Single language Verilog license
+; msimhdlsim Language neutral license for either Verilog or VHDL
+; msimhdlmix Second language only, language neutral license for either
+; Verilog or VHDL
+;
+; Directives to license manager can be set either as single value or as
+; space separated multi-values:
+; vhdl Immediately checkout and hold a VHDL license (i.e., one of
+; qhsimvh, msimhdlsim, or msimhdlmix)
+; vlog Immediately checkout and hold a Verilog license (i.e., one of
+; qhsimvl, msimhdlsim, or msimhdlmix)
+; plus Immediately checkout and hold a VHDL license and a Verilog license
+; noqueue Do not wait in the license queue when a license is not available
+; viewsim Try for viewer license but accept simulator license(s) instead
+; of queuing for viewer license (PE ONLY)
+; noviewer Disable checkout of msimviewer license feature (PE ONLY)
+; noslvhdl Disable checkout of qhsimvh license feature
+; noslvlog Disable checkout of qhsimvl license feature
+; nomix Disable checkout of msimhdlmix license feature
+; nolnl Disable checkout of msimhdlsim license feature
+; mixedonly Disable checkout of qhsimvh and qhsimvl license features
+; lnlonly Disable checkout of qhsimvh,qhsimvl, and msimhdlmix license features
+;
+; Examples (remove ";" comment character to activate licensing directives):
+; Single directive:
+; License = plus
+; Multi-directive (Note: space delimited directives):
+; License = noqueue plus
+
+; Severity level of a VHDL assertion message or of a SystemVerilog severity system task
+; which will cause a running simulation to stop.
+; VHDL assertions and SystemVerilog severity system task that occur with the
+; given severity or higher will cause a running simulation to stop.
+; This value is ignored during elaboration.
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+BreakOnAssertion = 3
+
+; Severity level of a tool message which will cause a running simulation to
+; stop. This value is ignored during elaboration. Default is to not break.
+; 0 = Note 1 = Warning 2 = Error 3 = Fatal
+;BreakOnMessage = 2
+
+; The class debug feature enables more visibility and tracking of class instances
+; during simulation. By default this feature is disabled (0). To enable this
+; feature set ClassDebug to 1.
+; ClassDebug = 1
+
+; Message Format conversion specifications:
+; %S - Severity Level of message/assertion
+; %R - Text of message
+; %T - Time of message
+; %D - Delta value (iteration number) of Time
+; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected
+; %i - Instance/Region/Signal pathname with Process name (if available)
+; %I - shorthand for one of these:
+; " %K: %i"
+; " %K: %i File: %F" (when path is not Process or Signal)
+; except that the %i in this case does not report the Process name
+; %O - Process name
+; %P - Instance/Region path without leaf process
+; %F - File name
+; %L - Line number; if assertion message, then line number of assertion or, if
+; assertion is in a subprogram, line from which the call is made
+; %u - Design unit name in form library.primary
+; %U - Design unit name in form library.primary(secondary)
+; %% - The '%' character itself
+;
+; If specific format for Severity Level is defined, use that format.
+; Else, for a message that occurs during elaboration:
+; -- Failure/Fatal message in VHDL region that is not a Process, and in
+; certain non-VHDL regions, uses MessageFormatBreakLine;
+; -- Failure/Fatal message otherwise uses MessageFormatBreak;
+; -- Note/Warning/Error message uses MessageFormat.
+; Else, for a message that occurs during runtime and triggers a breakpoint because
+; of the BreakOnAssertion setting:
+; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine;
+; -- otherwise uses MessageFormatBreak.
+; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat.
+;
+; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n"
+; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
+
+; Error File - alternate file for storing error messages
+; ErrorFile = error.log
+
+; Simulation Breakpoint messages
+; This flag controls the display of function names when reporting the location
+; where the simulator stops because of a breakpoint or fatal error.
+; Example with function name: # Break in Process ctr at counter.vhd line 44
+; Example without function name: # Break at counter.vhd line 44
+; Default value is 1.
+ShowFunctions = 1
+
+; Default radix for all windows and commands.
+; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned
+; Flags may be one of: enumnumeric, showbase, wreal
+DefaultRadix = hexadecimal
+DefaultRadixFlags = showbase
+; Set to 1 for make the signal_force VHDL and Verilog functions use the
+; default radix when processing the force value. Prior to 10.2 signal_force
+; used the default radix, now it always uses symbolic unless value explicitly indicates base
+;SignalForceFunctionUseDefaultRadix = 0
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; VSIM Shutdown file
+; Filename to save u/i formats and configurations.
+; ShutdownFile = restart.do
+; To explicitly disable auto save:
+; ShutdownFile = --disable-auto-save
+
+; Run simulator in batch mode as if -batch were specified on the command line if none of -c, -gui, or -i specified.
+; Simulator runs in interactive mode as if -i were specified if this option is 0. Default is 0.
+; BatchMode = 1
+
+; File for saving command transcript when -batch option used
+; This option is ignored when -c, -gui, or -i options are used or if BatchMode above is zero
+; default is unset so command transcript only goes to stdout for better performance
+; BatchTranscriptFile = transcript
+
+; File for saving command transcript, this option is ignored when -batch option is used
+TranscriptFile = transcript
+
+; Transcript file long line wrapping mode(s)
+; mode == 0 :: no wrapping, line recorded as is
+; mode == 1 :: wrap at first whitespace after WSColumn
+; or at Column.
+; mode == 2 :: wrap as above, but add continuation
+; character ('\') at end of each wrapped line
+;
+; WrapMode = 0
+; WrapColumn = 30000
+; WrapWSColumn = 27000
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example: sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Specify a unique path separator for the Signal Spy set of functions.
+; The default will be to use the PathSeparator variable.
+; Must not be the same character as DatasetSeparator.
+; SignalSpyPathSeparator = /
+
+; Used to control parsing of HDL identifiers input to the tool.
+; This includes CLI commands, vsim/vopt/vlog/vcom options,
+; string arguments to FLI/VPI/DPI calls, etc.
+; If set to 1, accept either Verilog escaped Id syntax or
+; VHDL extended id syntax, regardless of source language.
+; If set to 0, the syntax of the source language must be used.
+; Each identifier in a hierarchical name may need different syntax,
+; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or
+; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"
+; GenerousIdentifierParsing = 1
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Disable SystemVerilog assertion messages
+; IgnoreSVAInfo = 1
+; IgnoreSVAWarning = 1
+; IgnoreSVAError = 1
+; IgnoreSVAFatal = 1
+
+; Do not print any additional information from Severity System tasks.
+; Only the message provided by the user is printed along with severity
+; information.
+; SVAPrintOnlyUserMessage = 1;
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; Control the iteration of events when a VHDL signal is forced to a value
+; This flag can be set to honour the signal update event in next iteration,
+; the default is to update and propagate in the same iteration.
+; ForceSigNextIter = 1
+
+; Enable simulation statistics. Specify one or more arguments:
+; [all,none,time,cmd,msg,perf,verbose,list,kb,eor]
+; Add '-' to disable specific statistics. Default is [time,cmd,msg].
+; Stats = time,cmd,msg
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write. Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+; 0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+; 0 = unlimited
+ConcurrentFileLimit = 40
+
+; If nonzero, close files as soon as there is either an explicit call to
+; file_close, or when the file variable's scope is closed. When zero, a
+; file opened in append mode is not closed in case it is immediately
+; reopened in append mode; otherwise, the file will be closed at the
+; point it is reopened.
+; AppendClose = 1
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings when changing VHDL constants and generics
+; Default is 1 to generate warning messages
+; WarnConstantChange = 0
+
+; Turn off warnings from accelerated versions of the std_logic_arith,
+; std_logic_unsigned, and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from accelerated versions of the IEEE numeric_std
+; and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Use old-style (pre-6.6) VHDL FOR GENERATE statement iteration names
+; in the design hierarchy.
+; This style is controlled by the value of the GenerateFormat
+; value described next. Default is to use new-style names, which
+; comprise the generate statement label, '(', the value of the generate
+; parameter, and a closing ')'.
+; Set this to 1 to use old-style names.
+; OldVhdlForGenNames = 1
+
+; Control the format of the old-style VHDL FOR generate statement region
+; name for each iteration. Do not quote the value.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes. The %s represents
+; the generate statement label; the %d represents the generate parameter value
+; at a particular iteration (this is the position number if the generate parameter
+; is of an enumeration type). Embedded whitespace is allowed (but discouraged);
+; leading and trailing whitespace is ignored.
+; Application of the format must result in a unique region name over all
+; loop iterations for a particular immediately enclosing scope so that name
+; lookup can function properly. The default is %s__%d.
+; GenerateFormat = %s__%d
+
+; Enable more efficient logging of VHDL Variables.
+; Logging VHDL variables without this enabled, while possible, is very
+; inefficient. Enabling this will provide a more efficient logging methodology
+; at the expense of more memory usage. By default this feature is disabled (0).
+; To enabled this feature, set this variable to 1.
+; VhdlVariableLogging = 1
+
+; Enable logging of VHDL access type variables and their designated objects.
+; This setting will allow both variables of an access type ("access variables")
+; and their designated objects ("access objects") to be logged. Logging a
+; variable of an access type will automatically also cause the designated
+; object(s) of that variable to be logged as the simulation progresses.
+; Further, enabling this allows access objects to be logged by name. By default
+; this feature is disabled (0). To enable this feature, set this variable to 1.
+; Enabling this will automatically enable the VhdlVariableLogging feature also.
+; AccessObjDebug = 1
+
+; Make each VHDL package in a PDU has its own separate copy of the package instead
+; of sharing the package between PDUs. The default is to share packages.
+; To ensure that each PDU has its own set of packages, set this variable to 1.
+; VhdlSeparatePduPackage = 1
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper.
+; Use custom gcc compiler located at this path rather than the default path.
+; The path should point directly at a compiler executable.
+; DpiCppPath = <your-gcc-installation>/bin/gcc
+;
+; Specify the compiler version from the list of support GNU compilers.
+; examples 4.5.0, 4.7.4
+; DpiCppInstall = 4.7.4
+
+; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls.
+; The term "out-of-the-blue" refers to SystemVerilog export function calls
+; made from C functions that don't have the proper context setup
+; (as is the case when running under "DPI-C" import functions).
+; When this is enabled, one can call a DPI export function
+; (but not task) from any C code.
+; the setting of this variable can be one of the following values:
+; 0 : dpioutoftheblue call is disabled (default)
+; 1 : dpioutoftheblue call is enabled, but export call debug support is not available.
+; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available.
+; DpiOutOfTheBlue = 1
+
+; Specify whether continuous assignments are run before other normal priority
+; processes scheduled in the same iteration. This event ordering minimizes race
+; differences between optimized and non-optimized designs, and is the default
+; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set
+; ImmediateContinuousAssign to 0.
+; The default is 1 (enabled).
+; ImmediateContinuousAssign = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Which default VPI object model should the tool conform to?
+; The 1364 modes are Verilog-only, for backwards compatibility with older
+; libraries, and SystemVerilog objects are not available in these modes.
+;
+; In the absence of a user-specified default, the tool default is the
+; latest available LRM behavior.
+; Options for PliCompatDefault are:
+; VPI_COMPATIBILITY_VERSION_1364v1995
+; VPI_COMPATIBILITY_VERSION_1364v2001
+; VPI_COMPATIBILITY_VERSION_1364v2005
+; VPI_COMPATIBILITY_VERSION_1800v2005
+; VPI_COMPATIBILITY_VERSION_1800v2008
+;
+; Synonyms for each string are also recognized:
+; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995)
+; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001)
+; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005)
+; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005)
+; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008)
+
+
+; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005
+
+; Specify whether the Verilog system task $fopen or vpi_mcd_open()
+; will create directories that do not exist when opening the file
+; in "a" or "w" mode.
+; The default is 0 (do not create non-existent directories)
+; CreateDirForFileAccess = 1
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
+; DefaultRestartOptions = -force
+
+
+; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used.
+; Valid options include: all, none, verbose, disable, struct, reseed, msglog, trlog, certe.
+; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-".
+; The list of options must be delimited by commas, without spaces or tabs.
+;
+; Some examples
+; To turn on all available UVM-aware debug features:
+; UVMControl = all
+; To turn on the struct window, mesage logging, and transaction logging:
+; UVMControl = struct,msglog,trlog
+; To turn on all options except certe:
+; UVMControl = all,-certe
+; To completely disable all UVM-aware debug functionality:
+; UVMControl = disable
+
+; Specify the WildcardFilter setting.
+; A space separated list of object types to be excluded when performing
+; wildcard matches with log, wave, etc commands. The default value for this variable is:
+; "Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile"
+; See "Using the WildcardFilter Preference Variable" in the documentation for
+; details on how to use this variable and for descriptions of the filter types.
+WildcardFilter = Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile
+
+; Specify the WildcardSizeThreshold setting.
+; This integer setting specifies the size at which objects will be excluded when
+; performing wildcard matches with log, wave, etc commands. Objects of size equal
+; to or greater than the WildcardSizeThreshold will be filtered out from the wildcard
+; matches. The size is a simple calculation of number of bits or items in the object.
+; The default value is 8k (8192). Setting this value to 0 will disable the checking
+; of object size against this threshold and allow all objects of any size to be logged.
+WildcardSizeThreshold = 8192
+
+; Specify whether warning messages are output when objects are filtered out due to the
+; WildcardSizeThreshold. The default is 0 (no messages generated).
+WildcardSizeThresholdVerbose = 0
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit. Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time. When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit. Limit WLF file size, as closely as possible,
+; to the specified number of megabytes. If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends. A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Specify whether or not a WLF file should be optimized during
+; simulation. If set to 0, the WLF file will not be optimized.
+; The default is 1, optimize the WLF file.
+; WLFOptimize = 0
+
+; Specify the name of the WLF file.
+; The default is vsim.wlf
+; WLFFilename = vsim.wlf
+
+; Specify whether to lock the WLF file.
+; Locking the file prevents other invocations of ModelSim/Questa tools from
+; inadvertently overwriting the WLF file.
+; The default is 1, lock the WLF file.
+; WLFFileLock = 0
+
+; Specify the update interval for the WLF file in live simulation.
+; The interval is given in seconds.
+; The value is the smallest interval between WLF file updates. The WLF file
+; will be flushed (updated) after (at least) the interval has elapsed, ensuring
+; that the data is correct when viewed from a separate viewer.
+; A value of 0 means that no updating will occur.
+; The default value is 10 seconds.
+; WLFUpdateInterval = 10
+
+; Specify the WLF cache size limit for WLF files.
+; The value is given in megabytes. A value of 0 turns off the cache.
+; On non-Windows platforms the default WLFCacheSize setting is 2000 (megabytes).
+; On Windows, the default value is 1000 (megabytes) to help to avoid filling
+; process memory.
+; WLFSimCacheSize allows a different cache size to be set for a live simulation
+; WLF file, independent of post-simulation WLF file viewing. If WLFSimCacheSize
+; is not set, it defaults to the WLFCacheSize value.
+; WLFCacheSize = 2000
+; WLFSimCacheSize = 500
+
+; Specify the WLF file event collapse mode.
+; 0 = Preserve all events and event order. (same as -wlfnocollapse)
+; 1 = Only record values of logged objects at the end of a simulator iteration.
+; (same as -wlfcollapsedelta)
+; 2 = Only record values of logged objects at the end of a simulator time step.
+; (same as -wlfcollapsetime)
+; The default is 1.
+; WLFCollapseMode = 0
+
+; Specify whether WLF file logging can use threads on multi-processor machines.
+; If 0, no threads will be used; if 1, threads will be used if the system has
+; more than one processor.
+; WLFUseThreads = 1
+
+; Specify the size of objects that will trigger "large object" messages
+; at log/wave/list time. The size calculation of the object is the same as that
+; used by the WildcardSizeThreshold. The default LargeObjectSize size is 500,000.
+; Setting LargeObjectSize to 0 will disable these messages.
+; LargeObjectSize = 500000
+
+; Specify the depth of stack frames returned by $stacktrace([level]).
+; This depth will be picked up when the optional 'level' argument
+; is not specified or its value is not a positive integer.
+; StackTraceDepth = 100
+
+; Turn on/off undebuggable SystemC type warnings. Default is on.
+; ShowUndebuggableScTypeWarning = 0
+
+; Turn on/off unassociated SystemC name warnings. Default is off.
+; ShowUnassociatedScNameWarning = 1
+
+; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off.
+; ScShowIeeeDeprecationWarnings = 1
+
+; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off.
+; ScEnableScSignalWriteCheck = 1
+
+; Set SystemC default time unit.
+; Set to fs, ps, ns, us, ms, or sec with optional
+; prefix of 1, 10, or 100. The default is 1 ns.
+; The ScTimeUnit value is honored if it is coarser than Resolution.
+; If ScTimeUnit is finer than Resolution, it is set to the value
+; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
+; then the default time unit will be 1 ns. However if Resolution
+; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
+ScTimeUnit = ns
+
+; Set SystemC sc_main stack size. The stack size is set as an integer
+; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
+; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends
+; on the amount of data on the sc_main() stack and the memory required
+; to succesfully execute the longest function call chain of sc_main().
+ScMainStackSize = 10 Mb
+
+; Set SystemC thread stack size. The stack size is set as an integer
+; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
+; Gb(Giga-byte). The stack size for sc_thread depends
+; on the amount of data on the sc_thread stack and the memory required
+; to succesfully execute the thread.
+; ScStackSize = 1 Mb
+
+; Turn on/off execution of remainder of sc_main upon quitting the current
+; simulation session. If the cumulative length of sc_main() in terms of
+; simulation time units is less than the length of the current simulation
+; run upon quit or restart, sc_main() will be in the middle of execution.
+; This switch gives the option to execute the remainder of sc_main upon
+; quitting simulation. The drawback of not running sc_main till the end
+; is memory leaks for objects created by sc_main. If on, the remainder of
+; sc_main will be executed ignoring all delays. This may cause the simulator
+; to crash if the code in sc_main is dependent on some simulation state.
+; Default is on.
+ScMainFinishOnQuit = 1
+
+; Enable calling of the DPI export taks/functions from the
+; SystemC start_of_simulation() callback.
+; The default is off.
+; EnableDpiSosCb = 1
+
+
+; Set the SCV relationship name that will be used to identify phase
+; relations. If the name given to a transactor relation matches this
+; name, the transactions involved will be treated as phase transactions
+ScvPhaseRelationName = mti_phase
+
+; Customize the vsim kernel shutdown behavior at the end of the simulation.
+; Some common causes of the end of simulation are $finish (implicit or explicit),
+; sc_stop(), tf_dofinish(), and assertion failures.
+; This should be set to "ask", "exit", or "stop". The default is "ask".
+; "ask" -- In batch mode, the vsim kernel will abruptly exit.
+; In GUI mode, a dialog box will pop up and ask for user confirmation
+; whether or not to quit the simulation.
+; "stop" -- Cause the simulation to stay loaded in memory. This can make some
+; post-simulation tasks easier.
+; "exit" -- The simulation will abruptly exit without asking for any confirmation.
+; "final" -- Run SystemVerilog final blocks then behave as "stop".
+; Note: This variable can be overridden with the vsim "-onfinish" command line switch.
+OnFinish = ask
+
+; Print pending deferred assertion messages.
+; Deferred assertion messages may be scheduled after the $finish in the same
+; time step. Deferred assertions scheduled to print after the $finish are
+; printed before exiting with severity level NOTE since it's not known whether
+; the assertion is still valid due to being printed in the active region
+; instead of the reactive region where they are normally printed.
+; OnFinishPendingAssert = 1;
+
+; Print "simstats" result. Default is 0.
+; 0 == do not print simstats
+; 1 == print at end of simulation
+; 2 == print at end of each run command and end of simulation
+; PrintSimStats = 1
+
+; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Enable assertion counts. Default is off.
+; AssertionCounts = 1
+
+; Run simulator in assertion debug mode. Default is off.
+; AssertionDebug = 1
+
+; Turn on/off PSL/SVA/VHDL assertion enable. Default is on.
+; AssertionEnable = 0
+
+; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1.
+; Any positive integer, -1 for infinity.
+; AssertionLimit = 1
+
+; Turn on/off concurrent assertion pass log. Default is off.
+; Assertion pass logging is only enabled when assertion is browseable
+; and assertion debug is enabled.
+; AssertionPassLog = 1
+
+; Turn on/off PSL concurrent assertion fail log. Default is on.
+; The flag does not affect SVA
+; AssertionFailLog = 0
+
+; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on.
+; AssertionFailLocalVarLog = 0
+
+; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
+; 0 = Continue 1 = Break 2 = Exit
+; AssertionFailAction = 1
+
+; Enable the active thread monitor in the waveform display when assertion debug is enabled.
+; AssertionActiveThreadMonitor = 1
+
+; Control how many waveform rows will be used for displaying the active threads. Default is 5.
+; AssertionActiveThreadMonitorLimit = 5
+
+; Assertion thread limit after which assertion would be killed/switched off.
+; The default is -1 (unlimited). If the number of threads for an assertion go
+; beyond this limit, the assertion would be either switched off or killed. This
+; limit applies to only assert directives.
+;AssertionThreadLimit = -1
+
+; Action to be taken once the assertion thread limit is reached. Default
+; is kill. It can have a value of off or kill. In case of kill, all the existing
+; threads are terminated and no new attempts are started. In case of off, the
+; existing attempts keep on evaluating but no new attempts are started. This
+; variable applies to only assert directives.
+;AssertionThreadLimitAction = kill
+
+; Cover thread limit after which cover would be killed/switched off.
+; The default is -1 (unlimited). If the number of threads for a cover go
+; beyond this limit, the cover would be either switched off or killed. This
+; limit applies to only cover directives.
+;CoverThreadLimit = -1
+
+; Action to be taken once the cover thread limit is reached. Default
+; is kill. It can have a value of off or kill. In case of kill, all the existing
+; threads are terminated and no new attempts are started. In case of off, the
+; existing attempts keep on evaluating but no new attempts are started. This
+; variable applies to only cover directives.
+;CoverThreadLimitAction = kill
+
+
+; By default immediate assertions do not participate in Assertion Coverage calculations
+; unless they are executed. This switch causes all immediate assertions in the design
+; to participate in Assertion Coverage calculations, whether attempted or not.
+; UnattemptedImmediateAssertions = 0
+
+; By default immediate covers participate in Coverage calculations
+; whether they are attempted or not. This switch causes all unattempted
+; immediate covers in the design to stop participating in Coverage
+; calculations.
+; UnattemptedImmediateCovers = 0
+
+; By default pass action block is not executed for assertions on vacuous
+; success. The following variable is provided to enable execution of
+; pass action block on vacuous success. The following variable is only effective
+; if the user does not disable pass action block execution by using either
+; system tasks or CLI. Also there is a performance penalty for enabling
+; the following variable.
+;AssertionEnableVacuousPassActionBlock = 1
+
+; As per strict 1850-2005 PSL LRM, an always property can either pass
+; or fail. However, by default, Questa reports multiple passes and
+; multiple fails on top always/never property (always/never operator
+; is the top operator under Verification Directive). The reason
+; being that Questa reports passes and fails on per attempt of the
+; top always/never property. Use the following flag to instruct
+; Questa to strictly follow LRM. With this flag, all assert/never
+; directives will start an attempt once at start of simulation.
+; The attempt can either fail, match or match vacuously.
+; For e.g. if always is the top operator under assert, the always will
+; keep on checking the property at every clock. If the property under
+; always fails, the directive will be considered failed and no more
+; checking will be done for that directive. A top always property,
+; if it does not fail, will show a pass at end of simulation.
+; The default value is '0' (i.e. zero is off). For example:
+; PslOneAttempt = 1
+
+; Specify the number of clock ticks to represent infinite clock ticks.
+; This affects eventually!, until! and until_!. If at End of Simulation
+; (EOS) an active strong-property has not clocked this number of
+; clock ticks then neither pass or fail (vacuous match) is returned
+; else respective fail/pass is returned. The default value is '0' (zero)
+; which effectively does not check for clock tick condition. For example:
+; PslInfinityThreshold = 5000
+
+; Control how many thread start times will be preserved for ATV viewing for a given assertion
+; instance. Default is -1 (ALL).
+; ATVStartTimeKeepCount = -1
+
+; Turn on/off code coverage
+; CodeCoverage = 0
+
+; This option applies to condition and expression coverage UDP tables. It
+; has no effect unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp.
+; If this option is used and a match occurs in more than one row in the UDP table,
+; none of the counts for all matching rows is incremented. By default, counts are
+; incremented for all matching rows.
+; CoverCountAll = 1
+
+; Turn off automatic inclusion of VHDL integers in toggle coverage. Default
+; is to include them.
+; ToggleNoIntegers = 1
+
+; Set the maximum number of values that are collected for toggle coverage of
+; VHDL integers. Default is 100;
+; ToggleMaxIntValues = 100
+
+; Set the maximum number of values that are collected for toggle coverage of
+; Verilog real. Default is 100;
+; ToggleMaxRealValues = 100
+
+; Turn on automatic inclusion of Verilog integers in toggle coverage, except
+; for enumeration types. Default is to include them.
+; ToggleVlogIntegers = 0
+
+; Turn on automatic inclusion of Verilog real type in toggle coverage, except
+; for shortreal types. Default is to not include them.
+; ToggleVlogReal = 1
+
+; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays
+; and VHDL arrays-of-arrays in toggle coverage.
+; Default is to not include them.
+; ToggleFixedSizeArray = 1
+
+; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays,
+; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage.
+; This leads to a longer simulation time with bigger arrays covered with toggle coverage.
+; Default is 1024.
+; ToggleMaxFixedSizeArray = 1024
+
+; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized
+; one-dimensional packed vectors for toggle coverage. Default is 0.
+; TogglePackedAsVec = 0
+
+; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for
+; toggle coverage. Default is 0.
+; ToggleVlogEnumBits = 0
+
+; Turn off automatic inclusion of VHDL records in toggle coverage.
+; Default is to include them.
+; ToggleVHDLRecords = 0
+
+; Limit the widths of registers automatically tracked for toggle coverage. Default is 128.
+; For unlimited width, set to 0.
+; ToggleWidthLimit = 128
+
+; Limit the counts that are tracked for toggle coverage. When all edges for a bit have
+; reached this count, further activity on the bit is ignored. Default is 1.
+; For unlimited counts, set to 0.
+; ToggleCountLimit = 1
+
+; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3.
+; Following is the toggle coverage calculation criteria based on extended toggle mode:
+; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z').
+; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'.
+; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions.
+; ExtendedToggleMode = 3
+
+; Enable toggle statistics collection only for ports. Default is 0.
+; TogglePortsOnly = 1
+
+; Limit the counts that are tracked for Focussed Expression Coverage. When a bin has
+; reached this count, further tracking of the input patterns linked to it is ignored.
+; Default is 1. For unlimited counts, set to 0.
+; NOTE: Changing this value from its default value may affect simulation performance.
+; FecCountLimit = 1
+
+; Limit the counts that are tracked for UDP Coverage. When a bin has
+; reached this count, further tracking of the input patterns linked to it is ignored.
+; Default is 1. For unlimited counts, set to 0.
+; NOTE: Changing this value from its default value may affect simulation performance.
+; UdpCountLimit = 1
+
+; Control toggle coverage deglitching period. A period of 0, eliminates delta
+; cycle glitches. This is the default. The value of ToggleDeglitchPeriod needs to be either
+; 0 or a time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps".
+; ToggleDeglitchPeriod = 10.0ps
+
+; Turn on/off all PSL/SVA cover directive enables. Default is on.
+; CoverEnable = 0
+
+; Turn on/off PSL/SVA cover log. Default is off "0".
+; CoverLog = 1
+
+; Set "at_least" value for all PSL/SVA cover directives. Default is 1.
+; CoverAtLeast = 2
+
+; Set "limit" value for all PSL/SVA cover directives. Default is -1.
+; Any positive integer, -1 for infinity.
+; CoverLimit = 1
+
+; Specify the coverage database filename.
+; Default is "" (i.e. database is NOT automatically saved on close).
+; UCDBFilename = vsim.ucdb
+
+; Specify the maximum limit for the number of Cross (bin) products reported
+; in XML and UCDB report against a Cross. A warning is issued if the limit
+; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this
+; setting.
+; MaxReportRhsSVCrossProducts = 1000
+
+; Specify the override for the "auto_bin_max" option for the Covergroups.
+; If not specified then value from Covergroup "option" is used.
+; SVCoverpointAutoBinMax = 64
+
+; Specify the override for the value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then value
+; specified in the "option.cross_num_print_missing" is used. This
+; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
+; value specified by user in source file and any SVCrossNumPrintMissingDefault
+; specified in modelsim.ini.
+; SVCrossNumPrintMissing = 0
+
+; Specify whether to use the value of "cross_num_print_missing"
+; option in report and GUI for the Cross in Covergroups. If not specified then
+; cross_num_print_missing is ignored for creating reports and displaying
+; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing".
+; UseSVCrossNumPrintMissing = 0
+
+; Specify the threshold of Coverpoint wildcard bin value range size, above which
+; a warning will be triggered. The default is 4K -- 12 wildcard bits.
+; SVCoverpointWildCardBinValueSizeWarn = 4096
+
+; Specify the override for the value of "strobe" option for the
+; Covergroup Type. If not specified then value in "type_option.strobe"
+; will be used. This is runtime option which forces "strobe" to
+; user specified value and supersedes user specified values in the
+; SystemVerilog Code. NOTE: This also overrides the compile time
+; default value override specified using "SVCovergroupStrobeDefault"
+; SVCovergroupStrobe = 0
+
+; Override for explicit assignments in source code to "option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
+; SVCovergroupGoal = 100
+
+; Override for explicit assignments in source code to "type_option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
+; SVCovergroupTypeGoal = 100
+
+; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage()
+; builtin functions, and report. This setting changes the default values of
+; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3
+; behavior if explicit assignments are not made on option.get_inst_coverage and
+; type_option.merge_instances by the user. There are two vsim command line
+; options, -cvg63 and -nocvg63 to override this setting from vsim command line.
+; The default value of this variable from release 6.6 onwards is 0. This default
+; drives compliance with the clarified behavior in the IEEE 1800-2009 standard.
+; SVCovergroup63Compatibility = 0
+
+; Enforce the default behavior of covergroup get_coverage() builtin function, GUI
+; and report. This variable sets the default value of type_option.merge_instances.
+; There are two vsim command line options, -cvgmergeinstances and
+; -nocvgmergeinstances to override this setting from vsim command line.
+; The default value of this variable, -1 (don't care), allows the tool to determine
+; the effective value, based on factors related to capacity and optimization.
+; The type_option.merge_instances appears in the GUI and coverage reports as either
+; auto(1) or auto(0), depending on whether the effective value was determined to
+; be a 1 or a 0.
+; SVCovergroupMergeInstancesDefault = -1
+
+; Enable or disable generation of more detailed information about the sampling
+; of covergroup, cross, and coverpoints. It provides the details of the number
+; of times the covergroup instance and type were sampled, as well as details
+; about why covergroup, cross and coverpoint were not covered. A non-zero value
+; is to enable this feature. 0 is to disable this feature. Default is 0
+; SVCovergroupSampleInfo = 0
+
+; Specify the maximum number of Coverpoint bins in whole design for
+; all Covergroups.
+; MaxSVCoverpointBinsDesign = 2147483648
+
+; Specify maximum number of Coverpoint bins in any instance of a Covergroup, default is 2^10 bins
+; MaxSVCoverpointBinsInst = 1048576
+
+; Specify the maximum number of Cross bins in whole design for
+; all Covergroups.
+; MaxSVCrossBinsDesign = 2147483648
+
+; Specify maximum number of Cross bins in any instance of a Covergroup, default is 2^16 bins
+; MaxSVCrossBinsInst = 67108864
+
+; Specify whether vsim will collect the coverage data of zero-weight coverage items or not.
+; By default, this variable is set 0, in which case option.no_collect setting will take effect.
+; If this variable is set to 1, all zero-weight coverage items will not be saved.
+; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting
+; of this variable.
+; CvgZWNoCollect = 1
+
+; Specify a space delimited list of double quoted TCL style
+; regular expressions which will be matched against the text of all messages.
+; If any regular expression is found to be contained within any message, the
+; status for that message will not be propagated to the UCDB TESTSTATUS.
+; If no match is detected, then the status will be propagated to the
+; UCDB TESTSTATUS. More than one such regular expression text is allowed,
+; and each message text is compared for each regular expression in the list.
+; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message"
+
+; Set weight for all PSL/SVA cover directives. Default is 1.
+; CoverWeight = 2
+
+; Check vsim plusargs. Default is 0 (off).
+; 0 = Don't check plusargs
+; 1 = Warning on unrecognized plusarg
+; 2 = Error and exit on unrecognized plusarg
+; CheckPlusargs = 1
+
+; Load the specified shared objects with the RTLD_GLOBAL flag.
+; This gives global visibility to all symbols in the shared objects,
+; meaning that subsequently loaded shared objects can bind to symbols
+; in the global shared objects. The list of shared objects should
+; be whitespace delimited. This option is not supported on the
+; Windows or AIX platforms.
+; GlobalSharedObjectList = example1.so example2.so example3.so
+
+; Generate the stub definitions for the undefined symbols in the shared libraries being
+; loaded in the simulation. When this flow is turned on, the undefined symbols will not
+; prevent vsim from loading. Calling undefined symbols at runtime will cause fatal error.
+; The valid arguments are: on, off, verbose.
+; on : turn on the automatic generation of stub definitions.
+; off: turn off the flow. The undefined symbols will trigger an immediate load failure.
+; verbose: Turn on the flow and report the undefined symbols for each shared library.
+; NOTE: This variable can be overriden with vsim switch "-undefsyms".
+; The default is on.
+;
+; UndefSyms = off
+
+; Enable the support for checkpointing foreign C++ libraries.
+; The valid arguments are: 1 and 0.
+; 1 : turn on the support
+; 0 : turn off the support (default)
+; This option is not supported on the Windows platforms.
+;
+; AllowCheckpointCpp = 1
+
+; Initial seed for the random number generator of the root thread (SystemVerilog).
+; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch.
+; The default value is 0.
+; Sv_Seed = 0
+
+; Specify the solver "engine" that vsim will select for constrained random
+; generation.
+; Valid values are:
+; "auto" - automatically select the best engine for the current
+; constraint scenario
+; "bdd" - evaluate all constraint scenarios using the BDD solver engine
+; "act" - evaluate all constraint scenarios using the ACT solver engine
+; While the BDD solver engine is generally efficient with constraint scenarios
+; involving bitwise logical relationships, the ACT solver engine can exhibit
+; superior performance with constraint scenarios involving large numbers of
+; random variables related via arithmetic operators (+, *, etc).
+; NOTE: This variable can be overridden with the vsim "-solveengine" command
+; line switch.
+; The default value is "auto".
+; SolveEngine = auto
+
+; Specifies the maximum size that a dynamic array may be resized to by the
+; solver. If the solver attempts to resize a dynamic array to a size greater
+; than the specified limit, the solver will abort with an error.
+; The default value is 10000. A value of 0 indicates no limit.
+; SolveArrayResizeMax = 10000
+
+; Error message severity when normal randomize() and randomize(null) failures are detected.
+; Integer value up to two digits are allowed with each digit having the following legal values:
+; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+;
+; 1) When a value with two digits is used, the digit at tenth place (leftmost digit) represents
+; the severtity setting for normal randomize() calls. The digit at ones place (rightmost digit)
+; represents the setting for randomize(null) calls.
+;
+; 2) When a single digit value is used, the setting is applied to both normal randomize() call
+; and randomize(null) call.
+;
+; Example: -solvefailseverity=40 means:
+; fatal error for failed normal randomize() calls and NO error for failed randomize(null) calls.
+;
+; The default is 0 (no error).
+; SolveFailSeverity = 0
+
+; Error message severity for suppressible errors that are detected in a
+; solve/before constraint.
+; NOTE: This variable can be overridden with the vsim "-solvebeforeerrorseverity"
+; command line switch.
+; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+; The default is 3 (failure).
+; SolveBeforeErrorSeverity = 3
+
+; Error message severity for suppressible errors that are related to
+; solve engine capacity limits
+; NOTE: This variable can be overridden with the vsim "-solveengineerrorseverity"
+; command line switch.
+; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+; The default is 3 (failure).
+; SolveEngineErrorSeverity = 3
+
+; Enable/disable debug information for randomize() failures.
+; NOTE: This variable can be overridden with the vsim "-solvefaildebug" command
+; line switch.
+; The default is 0 (disabled). Set to 1 to enable basic debug (with no
+; performance penalty). Set to 2 for enhanced debug (will result in slower
+; runtime performance).
+; SolveFailDebug = 0
+
+; Upon encountering a randomize() failure, generate a simplified testcase that
+; will reproduce the failure. Optionally output the testcase to a file.
+; Testcases for 'no-solution' failures will only be produced if SolveFailDebug
+; is enabled (see above).
+; NOTE: This variable can be overridden with the vsim "-solvefailtestcase"
+; command line switch.
+; The default is OFF (do not generate a testcase). To enable testcase
+; generation, uncomment this variable. To redirect testcase generation to a
+; file, specify the name of the output file.
+; SolveFailTestcase =
+
+; Specify solver timeout threshold (in seconds). randomize() will fail if the
+; CPU time required to evaluate any randset exceeds the specified timeout.
+; The default value is 500. A value of 0 will disable timeout failures.
+; SolveTimeout = 500
+
+; Specify the maximum size of the solution graph generated by the BDD solver.
+; This value can be used to force the BDD solver to abort the evaluation of a
+; complex constraint scenario that cannot be evaluated with finite memory.
+; This value is specified in 1000s of nodes.
+; The default value is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxSize = 10000
+
+; Specify the maximum number of evaluations that may be performed on the
+; solution graph by the BDD solver. This value can be used to force the BDD
+; solver to abort the evaluation of a complex constraint scenario that cannot
+; be evaluated in finite time. This value is specified in 10000s of evaluations.
+; The default value is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxEval = 10000
+
+; Specify random sequence compatiblity with a prior letter release. This
+; option is used to get the same random sequences during simulation as
+; as a prior letter release. Only prior letter releases (of the current
+; number release) are allowed.
+; NOTE: Only those random sequence changes due to solver optimizations are
+; reverted by this variable. Random sequence changes due to solver bugfixes
+; cannot be un-done.
+; NOTE: This variable can be overridden with the vsim "-solverev" command
+; line switch.
+; Default value set to "" (no compatibility).
+; SolveRev =
+
+; Environment variable expansion of command line arguments has been depricated
+; in favor shell level expansion. Universal environment variable expansion
+; inside -f files is support and continued support for MGC Location Maps provide
+; alternative methods for handling flexible pathnames.
+; The following line may be uncommented and the value set to 1 to re-enable this
+; deprecated behavior. The default value is 0.
+; DeprecatedEnvironmentVariableExpansion = 0
+
+; Specify the memory threshold for the System Verilog garbage collector.
+; The value is the number of megabytes of class objects that must accumulate
+; before the garbage collector is run.
+; The GCThreshold setting is used when class debug mode is disabled to allow
+; less frequent garbage collection and better simulation performance.
+; The GCThresholdClassDebug setting is used when class debug mode is enabled
+; to allow for more frequent garbage collection.
+; GCThreshold = 100
+; GCThresholdClassDebug = 5
+
+; Turn on/off collapsing of bus ports in VCD dumpports output
+DumpportsCollapse = 1
+
+; Location of Multi-Level Verification Component (MVC) installation.
+; The default location is the product installation directory.
+MvcHome = $MODEL_TECH/..
+
+; Location of InFact installation. The default is $MODEL_TECH/../../infact
+;
+; InFactHome = $MODEL_TECH/../../infact
+
+; Initialize SystemVerilog enums using the base type's default value
+; instead of the leftmost value.
+; EnumBaseInit = 1
+
+; Suppress file type registration.
+; SuppressFileTypeReg = 1
+
+; Enable/disable non-LRM compliant SystemVerilog language extensions.
+; Valid extensions are:
+; altdpiheader - Alternative style function signature generated in DPI header",
+; cfce - generate an error if $cast fails as a function
+; cfmt - C like formatting for specifiers with '#' prefix ('%#x', '%#h')
+; dfsp - sets default format specifier as %p, if no format specifier is given for unpacked array in $display and related systasks
+; expdfmt - enable format string extensions for $display/$sformatf
+; extscan - support values greater than 32 bit for string builtin methods (atohex, atobin, atooct, atoi)
+; fmtcap - prints capital hex digits with %X/%H in display calls
+; iddp - ignore DPI disable protocol check
+; lfmt - zero-pad data if '0' prefixes width in format specifier (e.g. "%04h")
+; noexptc - ignore DPI export type name overloading check
+; realrand - support randomize() with real variables and constraints (Default)
+; thrdrngshfl - use the thread RNG for array.shuffle
+; SvExtensions = [+|-]<extension>[,[+|-]<extension>*]
+
+; Enable/disable non-LRM compliant SystemVerilog constrained-random language extensions.
+; Valid extensions are:
+; arraymode - consider rand_mode of unpacked array field independently from its elements
+; deepcheck - allow randomize(null) to recursively consider constraints from member rand class handles
+; funcback - enable function backtracking (ACT only)
+; nodist - interpret 'dist' constraint as 'inside' (ACT only)
+; noorder - ignore solve/before ordering constraints (ACT only)
+; promotedist - promote priority of 'dist' constraint if LHS has no solve/before
+; randindex - allow random index in constraint (Default)
+; randstruct - consider all fields of unpacked structs as 'rand'
+; skew - skew randomize results (ACT only)
+; strictstab - strict random stability
+; SvRandExtensions = [+|-]<extension>[,[+|-]<extension>*]
+
+; Controls the formatting of '%p' and '%P' conversion specification, used in $display
+; and similar system tasks.
+; 1. SVPrettyPrintFlags=I<n><S|T> use <n> spaces(S) or tabs(T) per indentation level.
+; The 'I' flag when present causes relevant data types to be expanded and indented into
+; a more readable format.
+; (e.g. SVPrettyPrintFlags=I4S will cause 4 spaces to be used per indentation level).
+; 2. SVPrettyPrintFlags=L<numLines> limits the output to <numLines> lines.
+; (e.g. SVPrettyPrintFlags=L20 will limit the output to 20 lines).
+; 3. SVPrettyPrintFlags=C<numChars> limits the output to <numChars> characters.
+; (e.g. SVPrettyPrintFlags=C256 will limit the output to 256 characters).
+; 4. SVPrettyPrintFlags=F<numFields> limits the output to <numFields> of relevant datatypes
+; (e.g. SVPrettyPrintFlags=F4 will limit the output to 4 fields of a structure).
+; 5. SVPrettyPrintFlags=E<numElements> limits the output to <numElements> of relevant datatypes
+; (e.g. SVPrettyPrintFlags=E50 will limit the output to 50 elements of an array).
+; 6. SVPrettyPrintFlags=D<depth> suppresses the output of sub-elements below <depth>.
+; (e.g. SVPrettyPrintFlags=D5 will suppresses the output of sub elements below a depth of 5).
+; 7. SVPrettyPrintFlags=R<specifier> shows the output of specifier %p as per the specifed radix.
+; It changes the output in $display and similar systasks. It does not affect formatted output functions ($displayh etc)).
+; (e.g. SVPrettyPrintFlags=Rb will show the output of %p specifier in binary format.
+; 8. Items 1-7 above can be combined as a comma separated list.
+; (e.g. SVPrettyPrintFlags=I4S,L20,C256,F4,E50,D5,Rb)
+; SVPrettyPrintFlags=I4S
+
+[lmc]
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software
+libsm = $MODEL_TECH/libsm.sl
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libsm = $MODEL_TECH/libsm.dll
+; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
+; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
+; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
+; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
+; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
+; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
+; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/linux.lib/libswift.so
+
+; The simulator's interface to Logic Modeling's hardware modeler SFI software
+libhm = $MODEL_TECH/libhm.sl
+; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
+; libhm = $MODEL_TECH/libhm.dll
+; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
+; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
+; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
+; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
+; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
+; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
+; Logic Modeling's hardware modeler SFI software (Windows NT)
+; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
+; Logic Modeling's hardware modeler SFI software (Linux)
+; libsfi = <sfi_dir>/lib/linux/libsfi.so
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; suppress can be used to achieve +nowarn<CODE> functionality
+; The format is: suppress = <CODE>,<msg number>,[<CODE>,<msg number>,...]
+; Examples:
+suppress = 8780 ;an explanation can be had by running: verror 8780
+; note = 3009
+; warning = 3033
+; error = 3010,3016
+; fatal = 3016,3033
+; suppress = 3009,3016,3601
+; suppress = 3009,CNNODP,3601,TFMPC
+; suppress = 8683,8684
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of Verilog display system task messages and
+; PLI/FLI print function call messages. The system tasks include
+; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They
+; also include the analogous file I/O tasks that write to STDOUT
+; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf,
+; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default
+; is to have messages appear only in the transcript. The other
+; settings are to send messages to the wlf file only (messages that
+; are recorded in the wlf file can be viewed in the MsgViewer) or
+; to both the transcript and the wlf file. The valid values are
+; tran {transcript only (default)}
+; wlf {wlf file only}
+; both {transcript and wlf file}
+; displaymsgmode = tran
+
+; Control transcripting of elaboration/runtime messages not
+; addressed by the displaymsgmode setting. The default is to
+; have messages appear only in the transcript. The other settings
+; are to send messages to the wlf file only (messages that are
+; recorded in the wlf file can be viewed in the MsgViewer) or to both
+; the transcript and the wlf file. The valid values are
+; tran {transcript only (default)}
+; wlf {wlf file only}
+; both {transcript and wlf file}
+; msgmode = tran
+
+; Controls number of displays of a particluar message
+; default value is 5
+; MsgLimitCount = 5
+
+[utils]
+; Default Library Type (while creating a library with "vlib")
+; 0 - legacy library using subdirectories for design units
+; 2 - flat library
+; DefaultLibType = 2
+
+; Flat Library Page Size (while creating a library with "vlib")
+; Set the size in bytes for flat library file pages. Libraries containing
+; very large files may benefit from a larger value.
+; FlatLibPageSize = 8192
+
+; Flat Library Page Cleanup Percentage (while creating a library with "vlib")
+; Set the percentage of total pages deleted before library cleanup can occur.
+; This setting is applied together with FlatLibPageDeleteThreshold.
+; FlatLibPageDeletePercentage = 50
+
+; Flat Library Page Cleanup Threshold (while creating a library with "vlib")
+; Set the number of pages deleted before library cleanup can occur.
+; This setting is applied together with FlatLibPageDeletePercentage.
+; FlatLibPageDeleteThreshold = 1000
+
diff --git a/compteur/simulation/pnr/compteur.wave.do b/compteur/simulation/pnr/compteur.wave.do
deleted file mode 100644
index 96fc0e5dcc8c5c2ffd51fec902d2e3e4fcbc2065..0000000000000000000000000000000000000000
--- a/compteur/simulation/pnr/compteur.wave.do
+++ /dev/null
@@ -1,24 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate /compteur_tb/clk
-add wave -noupdate /compteur_tb/rst_n
-add wave -noupdate {/compteur_tb/dut/rstn_sync[1]}
-add wave -noupdate /compteur_tb/dut/o_cnt
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {8064 ps} 0}
-quietly wave cursor active 1
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 0
-configure wave -timelineunits ns
-update
-WaveRestoreZoom {0 ps} {40530 ps}
diff --git a/compteur/simulation/run.do b/compteur/simulation/run.do
new file mode 100644
index 0000000000000000000000000000000000000000..cc992010f2b3b6263cb95893b9f5c96e9051b471
--- /dev/null
+++ b/compteur/simulation/run.do
@@ -0,0 +1,18 @@
+global tb
+global dut
+global vcd
+
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+
+log * -r
+add wave -r /*
+
+onerror { break }
+onbreak { quit -sim }
+
+vcd file $vcd
+vcd add -r /${tb}/${dut}/*
+
+run -all
+vcd flush
diff --git a/compteur/simulation/syn/compteur.wave.do b/compteur/simulation/syn/compteur.wave.do
deleted file mode 100644
index 8146711eab9679fbfce77f2a293ca2f47e9c1951..0000000000000000000000000000000000000000
--- a/compteur/simulation/syn/compteur.wave.do
+++ /dev/null
@@ -1,24 +0,0 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate /compteur_tb/clk
-add wave -noupdate /compteur_tb/rst_n
-add wave -noupdate {/compteur_tb/dut/rstn_sync[1]}
-add wave -noupdate /compteur_tb/dut/o_cnt
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {5364 ps} 0}
-quietly wave cursor active 1
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 100
-configure wave -griddelta 40
-configure wave -timeline 0
-configure wave -timelineunits ns
-update
-WaveRestoreZoom {0 ps} {40530 ps}
diff --git a/compteur/sources/compteur.vhd b/compteur/sources/compteur.vhd
index c7e93d77f58149d5a47d477f3c7a0905891c51c6..48000f2b4ca33398fdb10e34a54ff9a0a2639774 100644
--- a/compteur/sources/compteur.vhd
+++ b/compteur/sources/compteur.vhd
@@ -1,14 +1,14 @@
-------------------------------------------------------------------------------
--- Project : Tutoriels - Conception de circuits intégrés numériques
+-- Project Tutoriels - Conception de circuits intégrés numériques
-------------------------------------------------------------------------------
--- File : compteur.vhd
--- Author : Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
--- Lab : grm@polymtl
--- Date : 2019-07-24
+-- File compteur.vhd
+-- Author Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
+-- Lab grm@polymtl
+-- Date 2019-10-02
-------------------------------------------------------------------------------
--- Description: Compteur BCD Ã 1 chiffre (4 bits)
+-- Brief Compteur BCD Ã 1 chiffre (4 bits)
-------------------------------------------------------------------------------
-library ieee;
+library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
@@ -27,24 +27,24 @@ architecture beh of compteur is
signal cnt : unsigned(3 downto 0);
signal rstn_sync : std_logic_vector(1 downto 0);
alias rstn : std_logic is rstn_sync(1);
-
+
begin
- -- Output
+ -- Output
o_cnt <= std_logic_vector(cnt);
-- Reset synchronizer
p_rstn: process (i_clk)
- begin
+ begin
if (i_rstn = '0') then
rstn_sync <= (others => '0');
elsif rising_edge(i_clk) then
rstn_sync(0) <= '1';
rstn_sync(1) <= rstn_sync(0);
- end if;
+ end if;
end process p_rstn;
- -- Main process with asynchronous reset
+ -- Main process with asynchronous reset
p_bcd: process (i_clk, rstn)
begin
if (rstn = '0') then
@@ -59,5 +59,5 @@ begin
end if;
end if;
end process p_bcd;
-
+
end architecture beh;
diff --git a/compteur/sources/compteur_tb.vhd b/compteur/sources/compteur_tb.vhd
index bb9f4d5b675fc842a805484ee74b8b234564e3eb..4d8280a136f2ce5033300ceec02f127c57c9c059 100644
--- a/compteur/sources/compteur_tb.vhd
+++ b/compteur/sources/compteur_tb.vhd
@@ -1,24 +1,24 @@
-------------------------------------------------------------------------------
--- Project : Tutoriels - Conception de circuits intégrés numériques
+-- Project Tutoriels - Conception de circuits intégrés numériques
-------------------------------------------------------------------------------
--- File : compteur_tb.vhd
--- Author : Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
--- Lab : grm@polymtl
--- Date : 2019-07-24
+-- File compteur_tb.vhd
+-- Author Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
+-- Lab grm@polymtl
+-- Date 2019-10-02
-------------------------------------------------------------------------------
--- Description: Banc d'essai du compteur BCD
+-- Brief Banc d'essai du compteur BCD
-------------------------------------------------------------------------------
-library ieee;
+library ieee;
use ieee.std_logic_1164.all;
library std;
-use std.textio.all;
+use std.textio.all;
use std.env.all;
library work;
use work.all;
-entity compteur_tb is
+entity compteur_tb is
end compteur_tb;
architecture tb of compteur_tb is
@@ -30,55 +30,80 @@ architecture tb of compteur_tb is
i_en : in std_logic;
o_cnt : out std_logic_vector(3 downto 0));
end component compteur;
-
- signal clk : std_logic := '0';
- signal rst_n : std_logic := '0';
- signal en : std_logic := '0';
- signal cnt : std_logic_vector(3 downto 0);
- constant PERIOD : time := 1 ns;
+ signal clk : std_logic := '0';
+ signal clk_en : std_logic := '0';
+ signal rstn : std_logic := '0';
+ signal rst_en : std_logic := '0';
+ signal en : std_logic := '0';
+ signal cnt : std_logic_vector(3 downto 0);
+
+ constant PERIOD : time := 1250 ps;
constant TB_LOOP : positive := 2;
- constant EXPECTED : std_logic_vector(3 downto 0) := "0011";
-
+ constant EXPECTED : std_logic_vector(3 downto 0) := "0100";
+
begin
-
-- Clock
- clk <= not clk after PERIOD / 2;
+ clk <= not clk after PERIOD/2 when clk_en = '1' else '0';
+
+ -- Reset
+ p_rst : process(clk)
+ begin
+ if falling_edge(clk) then
+ if rst_en = '1' then
+ rstn <= not rstn;
+ end if;
+ end if;
+ end process p_rst;
-- DUT
dut: compteur
port map (
i_clk => clk,
- i_rstn => rst_n,
+ i_rstn => rstn,
i_en => en,
o_cnt => cnt);
-- Main TB process
p_main : process
begin
- report "SIMULATION STARTS";
+ report "BEGIN SIMULATION";
+
+ -- Start the clock after 2 period to let the Xs settle.
+ wait for 2*PERIOD;
+ clk_en <= '1';
for i in 0 to TB_LOOP-1 loop
- en <= '0';
- rst_n <= '0';
- wait for 2.3 * PERIOD;
- rst_n <= '1';
- en <= '1';
+
+ -- Toggle Reset
+ wait until rising_edge(clk);
+ rst_en <= '1';
+ wait for PERIOD;
+ rst_en <= '0';
+ en <= '1';
+
+ -- Count 15 cycles
wait for 15 * PERIOD;
- en <= '0';
+ en <= '0';
- -- Assertion
- wait for 1*PERIOD;
+ -- Check final value
+ wait for PERIOD;
assert cnt = EXPECTED
report " cnt = " & to_hstring(cnt) & ", should be = " & to_hstring(EXPECTED)
severity WARNING;
- wait for 1*PERIOD;
-
+ wait for PERIOD;
+
+ -- Toggle reset
+ rst_en <= '1';
+ wait for PERIOD;
+ rst_en <= '0';
+ wait for PERIOD;
+
end loop;
-
+
report "SIMULATION ENDS";
- stop;
+ finish;
end process p_main;
-
+
end architecture tb;