diff --git a/sources/dft_compteur_tb.vhd b/sources/dft_compteur_tb.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..4b1d0de6807a91554a1db055f97c11fd40395390
--- /dev/null
+++ b/sources/dft_compteur_tb.vhd
@@ -0,0 +1,136 @@
+-------------------------------------------------------------------------------
+-- Project  Tutoriels - Conception de circuits intégrés numériques
+-------------------------------------------------------------------------------
+-- File     compteur_tb.vhd
+-- Author   Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
+-- Lab      grm@polymtl
+-- Date     2019-10-02
+-------------------------------------------------------------------------------
+-- Brief    Banc d'essai du compteur BCD
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+
+library std;
+use std.textio.all;
+use std.env.all;
+
+library work;
+use work.all;
+
+entity compteur_tb is
+end compteur_tb;
+
+architecture tb of compteur_tb is
+
+  component top is
+    port (
+      i_clk       : in  std_logic;
+      i_rstn      : in  std_logic;
+      i_en        : in  std_logic;
+      i_scan_en   : in  std_logic;
+      i_test_mode : in  std_logic;
+      i_tdi       : in  std_logic;
+      o_cnt       : out std_logic_vector(3 downto 0);
+      o_tdo       : out std_logic);
+  end component top;
+
+  signal clk    : std_logic := '0';
+  signal clk_en : std_logic := '0';
+  signal rstn   : std_logic := '0';
+  signal rst_en : std_logic := '0';
+  signal en     : std_logic := '0';
+  signal cnt    : std_logic_vector(3 downto 0);
+
+  constant PERIOD   : time                         := 1250 ps;
+  constant TB_LOOP  : positive                     := 2;
+  constant EXPECTED : std_logic_vector(3 downto 0) := "0101";
+
+begin
+
+  -- Clock
+  clk <= not clk after PERIOD/2 when clk_en = '1' else '0';
+
+  -- Reset
+  p_rst : process(clk)
+  begin
+    if falling_edge(clk) then
+      if rst_en = '1' then
+        rstn <= not rstn;
+      end if;
+    end if;
+  end process p_rst;
+
+  -- DUT
+  dut : top
+    port map (
+      i_clk       => clk,
+      i_rstn      => rstn,
+      i_en        => en,
+      i_scan_en   => '0',
+      i_test_mode => '0',
+      i_tdi       => '0',
+      o_cnt       => cnt,
+      o_tdo       => open);
+
+  -- Main TB process
+  p_main : process
+  begin
+    report "BEGIN SIMULATION";
+
+    -- Start the clock after 2 period to let the Xs settle.
+    wait for 2*PERIOD;
+    clk_en <= '1';
+
+    for i in 0 to TB_LOOP-1 loop
+
+      -- Toggle Reset
+      wait until falling_edge(clk);
+      rst_en <= '1';
+      wait for PERIOD;
+      rst_en <= '0';
+      wait for 4*PERIOD;
+      en     <= '1';
+
+      -- Count 15 cycles
+      wait for 15 * PERIOD;
+      en <= '0';
+
+      -- Check final value
+      wait for PERIOD;
+      assert cnt = EXPECTED
+        report " cnt = " & to_hstring(cnt) & ", should be = " & to_hstring(EXPECTED)
+        severity warning;
+      wait for PERIOD;
+
+      -- Toggle reset
+      rst_en <= '1';
+      wait for PERIOD;
+      rst_en <= '0';
+      wait for PERIOD;
+
+    end loop;
+
+    report "SIMULATION ENDS";
+    finish;
+  end process p_main;
+
+end architecture tb;
+
+-----------------------------------------------------------------------------
+-- CONFIGURATIONS
+-----------------------------------------------------------------------------
+configuration c_dft of compteur_tb is
+  for tb
+    for dut : top
+      use entity work.top(dft);
+    end for;
+  end for;
+end configuration;
+configuration c_rtl of compteur_tb is
+  for tb
+    for dut : top
+      use entity work.top(rtl);
+    end for;
+  end for;
+end configuration;
diff --git a/sources/dft_compteur_top.vhd b/sources/dft_compteur_top.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0801e229d667d0c30ea867488893d656a2012998
--- /dev/null
+++ b/sources/dft_compteur_top.vhd
@@ -0,0 +1,77 @@
+-------------------------------------------------------------------------------
+-- Project  Tutoriels - Conception de circuits intégrés numériques
+-------------------------------------------------------------------------------
+-- File     top.vhd
+-- Author   Erika Miller-Jolicoeur <erika.miller-jolicoeur@polymtl.ca>
+-- Lab      grm@polymtl
+-- Date     2020-07-27
+-------------------------------------------------------------------------------
+-- Brief    Enveloppe pour instancier correctement le compteur avec ou sans
+--          chaîne à balayage
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+
+library work;
+use work.all;
+
+entity top is
+  port (
+    i_clk       : in  std_logic;
+    i_rstn      : in  std_logic;
+    i_en        : in  std_logic;
+    i_scan_en   : in  std_logic;
+    i_test_mode : in  std_logic;
+    i_tdi       : in  std_logic;
+    o_cnt       : out std_logic_vector(3 downto 0);
+    o_tdo       : out std_logic);
+end;
+
+architecture dft of top is
+  component compteur is
+    port (
+      i_clk       : in  std_logic;
+      i_rstn      : in  std_logic;
+      i_en        : in  std_logic;
+      i_scan_en   : in  std_logic;
+      i_test_mode : in  std_logic;
+      i_tdi       : in  std_logic;
+      o_cnt       : out std_logic_vector(3 downto 0);
+      o_tdo       : out std_logic);
+  end component compteur;
+begin
+  -- Netlist DFT
+  m_compteur : compteur
+    port map (
+      i_clk       => i_clk,
+      i_rstn      => i_rstn,
+      i_en        => i_en,
+      i_scan_en   => i_scan_en,
+      i_test_mode => i_test_mode,
+      i_tdi       => i_tdi,
+      o_cnt       => o_cnt,
+      o_tdo       => o_tdo);
+
+end architecture dft;
+
+architecture rtl of top is
+
+  component compteur is
+    port (
+      i_clk  : in  std_logic;
+      i_rstn : in  std_logic;
+      i_en   : in  std_logic;
+      o_cnt  : out std_logic_vector(3 downto 0));
+  end component compteur;
+
+begin
+  -- Compteur RTL
+  m_compteur : compteur
+    port map (
+      i_clk  => i_clk,
+      i_rstn => i_rstn,
+      i_en   => i_en,
+      o_cnt  => o_cnt);
+
+  o_tdo <= '0';
+end architecture rtl;