diff --git a/compteur/constraints/compteur.syn.sdc b/compteur/constraints/compteur.syn.sdc
index 464c2551bbf841fa2a8e647cfec3f7f1784dddae..7008177c942e18e8d94089e33b2825c2c6cbd6fa 100644
--- a/compteur/constraints/compteur.syn.sdc
+++ b/compteur/constraints/compteur.syn.sdc
@@ -1,6 +1,6 @@
# ####################################################################
-# Created by Genus(TM) Synthesis Solution 17.10-p007_1 on Sun Mar 31 20:02:09 EDT 2019
+# Created by Genus(TM) Synthesis Solution 17.10-p007_1 on Tue Sep 10 10:42:42 EDT 2019
# ####################################################################
diff --git a/compteur/constraints/mmmc.tcl b/compteur/constraints/mmmc.tcl
index 47b3540d9f1e459606d9ce949b2ae317d3c2621e..4c37e84ee79f19a31e03ec97620abf9a2b5d4e78 100644
--- a/compteur/constraints/mmmc.tcl
+++ b/compteur/constraints/mmmc.tcl
@@ -1,11 +1,10 @@
#-----------------------------------------------------------------------------
-# Project : ELE8304 : Circuits intégrés à très grande échelle
+# Project : Tutoriels - Conception de circuits intégrés numériques
#-----------------------------------------------------------------------------
# File : mmmc.tcl
-# Author : Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
-# Lab : grm@polymtl
-# Created : 2018-06-22
-# Last update: 2019-03-29
+# Authors : Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
+# Lab : GRM - Polytechnique Montréal
+# Date : <2019-07-24 Wed>
#-----------------------------------------------------------------------------
# Description: Fichier de configuration "Multi-Mode Multi-Corner"
# pour le placement et routage du compteur BCD
diff --git a/compteur/constraints/timing.sdc b/compteur/constraints/timing.sdc
index affe47ca7d3295c068caf2897f03989b7fc3795f..b3d3f9252cae84793c1bc86c1f9f3735b25e95f6 100644
--- a/compteur/constraints/timing.sdc
+++ b/compteur/constraints/timing.sdc
@@ -1,11 +1,10 @@
#-----------------------------------------------------------------------------
-# Project : ELE8304 : Circuits intégrés à très grande échelle
+# Project : Tutoriels - Conception de circuits intégrés numériques
#-----------------------------------------------------------------------------
# File : timing.sdc
-# Author : Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
-# Lab : grm@polymtl
-# Created : 2018-06-22
-# Last update: 2018-09-07
+# Authors : Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
+# Lab : GRM - Polytechnique Montréal
+# Date : <2019-07-24 Wed>
#-----------------------------------------------------------------------------
# Description: Fichier de contraintes
#-----------------------------------------------------------------------------
diff --git a/compteur/implementation/pnr/.gitignore b/compteur/implementation/pnr/.gitignore
index ef359a4beb135ebe88e34ae9be9685bb2671ec45..cfc93770aa0858c9541487731d87e8919bba6883 100644
--- a/compteur/implementation/pnr/.gitignore
+++ b/compteur/implementation/pnr/.gitignore
@@ -3,7 +3,9 @@
*.cmd
*.old
*.setpower
+.powerAnalysis.pinfo
+preferred_layer_short_segment.rpt
.cadence/
liboa/
reports/cts/
-reports/power/
\ No newline at end of file
+reports/power/
diff --git a/compteur/implementation/pnr/cds.lib b/compteur/implementation/pnr/cds.lib
index 8e2ad365481c694207f294d07a5d562e9f05a05f..7dc594c3d589b57feb0b86354e579b5b2e4ef65b 100644
--- a/compteur/implementation/pnr/cds.lib
+++ b/compteur/implementation/pnr/cds.lib
@@ -1,16 +1,15 @@
#-----------------------------------------------------------------------------
-# Project : ELE8304 : Circuits intégrés à très grande échelle
+# Project : Tutoriels - Conception de circuits intégrés numériques
#-----------------------------------------------------------------------------
# File : cds.lib
-# Author : Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
-# Lab : grm@polymtl
-# Created : 2018-06-22
-# Last update: 2019-03-29
+# Authors : Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
+# Lab : GRM - Polytechnique Montréal
+# Date : <2019-07-24 Wed>
#-----------------------------------------------------------------------------
# Description: Configuration des librairies pour les outils Cadence
#-----------------------------------------------------------------------------
-DEFINE gpdk045 ${KIT_HOME}/tech/gpdk045/gpdk045
-DEFINE gsclib045_tech ${KIT_HOME}/tech/gsclib045/gsclib045_tech/oa22/gsclib045_tech
-DEFINE gsclib045 ${KIT_HOME}/tech/gsclib045/gsclib045/oa22/gsclib045
-DEFINE giolib045 ${KIT_HOME}/tech/giolib045/giolib045/oa22/giolib045
-DEFINE liboa liboa
\ No newline at end of file
+DEFINE gpdk045 ${KIT_GPDK}/gpdk045
+DEFINE gsclib045_tech ${KIT_SCLIB}/gsclib045_tech/oa22/gsclib045_tech
+DEFINE gsclib045 ${KIT_SCLIB}/gsclib045/oa22/gsclib045
+DEFINE giolib045 ${KIT_IOLIB}/giolib045/oa22/giolib045
+DEFINE liboa liboa
diff --git a/compteur/implementation/pnr/netlist/compteur.pnr.phy.v b/compteur/implementation/pnr/netlist/compteur.pnr.phy.v
index 53565bf82103ccfd17a0032add366c0a22030cc1..ac7533186f58814a56870b202f32ae3440eb89a0 100644
--- a/compteur/implementation/pnr/netlist/compteur.pnr.phy.v
+++ b/compteur/implementation/pnr/netlist/compteur.pnr.phy.v
@@ -2,9 +2,9 @@
###############################################################
# Generated by: Cadence Innovus 17.11-s080_1
# OS: Linux x86_64(Host ID pcys41)
-# Generated on: Fri Mar 29 20:17:16 2019
+# Generated on: Tue Sep 10 10:50:11 2019
# Design: compteur
-# Command: saveNetlist -phys /export/tmp/fiorentino/Projects/vlsi_numerique/compteur/implementation/pnr/netlist/compteur.pnr.phy.v
+# Command: saveNetlist -phys /export/tmp/fiorentino/Projects/grm/tutoriel_numerique/compteur/implementation/pnr/netlist/compteur.pnr.phy.v
###############################################################
*/
module BUFX20 (
@@ -191,7 +191,7 @@ module AND2X1 (
endmodule
// Generated by Cadence Genus(TM) Synthesis Solution 17.10-p007_1
-// Generated on: Mar 29 2019 17:29:54 EDT (Mar 29 2019 21:29:54 UTC)
+// Generated on: Sep 10 2019 10:42:42 EDT (Sep 10 2019 14:42:42 UTC)
// Verification Directory fv/compteur
module compteur (
i_clk,
diff --git a/compteur/implementation/pnr/netlist/compteur.pnr.sdf b/compteur/implementation/pnr/netlist/compteur.pnr.sdf
index 5e792902adeef211fbc72d91651427087d7d5ebd..6bdf8d9844ef6cbbf3b76bc69ecb4c04442a7e63 100644
--- a/compteur/implementation/pnr/netlist/compteur.pnr.sdf
+++ b/compteur/implementation/pnr/netlist/compteur.pnr.sdf
@@ -1,7 +1,7 @@
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "compteur")
- (DATE "Fri Mar 29 20:17:16 2019")
+ (DATE "Tue Sep 10 10:50:11 2019")
(VENDOR "Cadence Design Systems, Inc.")
(PROGRAM "Innovus")
(VERSION "v17.11-s080_1 ((64bit) 08/04/2017 11:13 (Linux 2.6.18-194.el5))")
diff --git a/compteur/implementation/pnr/netlist/compteur.pnr.v b/compteur/implementation/pnr/netlist/compteur.pnr.v
index 6553280d2d2a7423ecf685328042eb867215cca3..201ff5247e16827dbff67e994ed9e8a4ebf9f5b7 100644
--- a/compteur/implementation/pnr/netlist/compteur.pnr.v
+++ b/compteur/implementation/pnr/netlist/compteur.pnr.v
@@ -2,13 +2,13 @@
###############################################################
# Generated by: Cadence Innovus 17.11-s080_1
# OS: Linux x86_64(Host ID pcys41)
-# Generated on: Fri Mar 29 20:17:16 2019
+# Generated on: Tue Sep 10 10:50:11 2019
# Design: compteur
-# Command: saveNetlist /export/tmp/fiorentino/Projects/vlsi_numerique/compteur/implementation/pnr/netlist/compteur.pnr.v
+# Command: saveNetlist /export/tmp/fiorentino/Projects/grm/tutoriel_numerique/compteur/implementation/pnr/netlist/compteur.pnr.v
###############################################################
*/
// Generated by Cadence Genus(TM) Synthesis Solution 17.10-p007_1
-// Generated on: Mar 29 2019 17:29:54 EDT (Mar 29 2019 21:29:54 UTC)
+// Generated on: Sep 10 2019 10:42:42 EDT (Sep 10 2019 14:42:42 UTC)
// Verification Directory fv/compteur
module compteur (
i_clk,
diff --git a/compteur/implementation/pnr/reports/compteur.con.rpt b/compteur/implementation/pnr/reports/compteur.con.rpt
index afa651c2b093efb580a64a4a2db53d3b91da4d6f..00e69d41f684dfa3f43fad16ee9759e9a68e3bab 100644
--- a/compteur/implementation/pnr/reports/compteur.con.rpt
+++ b/compteur/implementation/pnr/reports/compteur.con.rpt
@@ -1,11 +1,11 @@
###############################################################
# Generated by: Cadence Innovus 17.11-s080_1
# OS: Linux x86_64(Host ID pcys41)
-# Generated on: Fri Mar 29 20:17:15 2019
+# Generated on: Tue Sep 10 10:50:10 2019
# Design: compteur
-# Command: verifyConnectivity -type all -error 1000 -warning 50 -report /export/tmp/fiorentino/Projects/vlsi_numerique/compteur/implementation/pnr/reports/compteur.con.rpt
+# Command: verifyConnectivity -type all -error 1000 -warning 50 -report /export/tmp/fiorentino/Projects/grm/tutoriel_numerique/compteur/implementation/pnr/reports/compteur.con.rpt
###############################################################
-Verify Connectivity Report is created on Fri Mar 29 20:17:15 2019
+Verify Connectivity Report is created on Tue Sep 10 10:50:10 2019
diff --git a/compteur/implementation/pnr/reports/compteur.drc.rpt b/compteur/implementation/pnr/reports/compteur.drc.rpt
index 0ef985437de983755018c42540985427784b0241..57e70cbef8f097d7ca905f574b1e71b78e25a794 100644
--- a/compteur/implementation/pnr/reports/compteur.drc.rpt
+++ b/compteur/implementation/pnr/reports/compteur.drc.rpt
@@ -1,11 +1,11 @@
###############################################################
# Generated by: Cadence Innovus 17.11-s080_1
# OS: Linux x86_64(Host ID pcys41)
-# Generated on: Fri Mar 29 20:17:15 2019
+# Generated on: Tue Sep 10 10:50:10 2019
# Design: compteur
# Command: verify_drc
###############################################################
-#set_verify_drc_mode -report /export/tmp/fiorentino/Projects/vlsi_numerique/compteur/implementation/pnr/reports/compteur.drc.rpt
+#set_verify_drc_mode -report /export/tmp/fiorentino/Projects/grm/tutoriel_numerique/compteur/implementation/pnr/reports/compteur.drc.rpt
No DRC violations were found
diff --git a/compteur/implementation/pnr/reports/compteur.dyn.rpt b/compteur/implementation/pnr/reports/compteur.dyn.rpt
index 32af594671d80f4b3ef5e0fcbb524a9fb3483d8f..e5e5326751de1de0e8e0a25fbb12f2ad4db9535a 100644
--- a/compteur/implementation/pnr/reports/compteur.dyn.rpt
+++ b/compteur/implementation/pnr/reports/compteur.dyn.rpt
@@ -2,24 +2,24 @@
* Voltus Power Analysis - Power Calculator - Version v16.16-s020_1 64-bit (05/03/2017 02:27:51)
* Copyright 2007, Cadence Design Systems, Inc.
*
-* Date & Time: 2019-Mar-29 20:33:04 (2019-Mar-30 00:33:04 GMT)
+* Date & Time: 2019-Sep-10 11:33:16 (2019-Sep-10 15:33:16 GMT)
*
*----------------------------------------------------------------------------------------
*
* Design: compteur
*
* Liberty Libraries used:
-* /CMC/kits/AMSKIT616_GPDK/tech/gsclib045/gsclib045/timing/fast_vdd1v0_basicCells.lib
+* /CMC/kits/GPDK45/gsclib045/gsclib045/timing/fast_vdd1v0_basicCells.lib
*
* Power Domain used:
* Rail: VDD Voltage: 1.1
*
* DEF Files used:
-* /tmp/ssv_tmpdir_32486_AXsV5R/eps_out_32486.def.gz
+* /tmp/ssv_tmpdir_30932_IDtqud/eps_out_30932.def.gz
*
* Switching Activity File used:
-* /export/tmp/fiorentino/Projects/vlsi_numerique/compteur/simulation/pnr/compteur.pnr.vcd
-* Vcd Window used(Start Time, Stop Time): (0,38500)
+* /export/tmp/fiorentino/Projects/grm/tutoriel_numerique/compteur/simulation/pnr/compteur.pnr.vcd
+* Vcd Window used(Start Time, Stop Time): (0,39)
* Vcd Scale Factor: 1
* * Design annotation coverage: 36/36 = 100%
*
@@ -39,7 +39,7 @@
*
* Time Units = 1e-09 secs
*
-* report_power -output /export/tmp/fiorentino/Projects/vlsi_numerique/compteur/implementation/pnr/reports -format detailed -report_prefix compteur.dyn
+* report_power -output /export/tmp/fiorentino/Projects/grm/tutoriel_numerique/compteur/implementation/pnr/reports/power -format detailed -report_prefix compteur.dyn
*
-----------------------------------------------------------------------------------------
diff --git a/compteur/implementation/pnr/reports/compteur.stat.rpt b/compteur/implementation/pnr/reports/compteur.stat.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..734c02f18d727e2050db693e37078a3eee395871
--- /dev/null
+++ b/compteur/implementation/pnr/reports/compteur.stat.rpt
@@ -0,0 +1,83 @@
+*----------------------------------------------------------------------------------------
+* Voltus IC Power Integrity Solution 16.16-s051_1 (64bit) 05/16/2017 12:06 (Linux 2.6.18-194.el5)
+*
+*
+* Date & Time: 2019-Sep-10 11:03:52 (2019-Sep-10 15:03:52 GMT)
+*
+*----------------------------------------------------------------------------------------
+*
+* Design: compteur
+*
+* Liberty Libraries used:
+* av_fast: /CMC/kits/GPDK45/gsclib045/gsclib045/timing/fast_vdd1v0_basicCells.lib
+*
+* Power Domain used:
+* Rail: VDD Voltage: 1.1
+*
+* Power View : av_fast
+*
+* User-Defined Activity : N.A.
+*
+* Activity File: N.A.
+*
+* Hierarchical Global Activity: N.A.
+*
+* Global Activity: N.A.
+*
+* Sequential Element Activity: N.A.
+*
+* Primary Input Activity: 0.200000
+*
+* Default icg ratio: N.A.
+*
+* Global Comb ClockGate Ratio: N.A.
+*
+* Power Units = 1mW
+*
+* Time Units = 1e-09 secs
+*
+* report_power -output /export/tmp/fiorentino/Projects/grm/tutoriel_numerique/compteur/implementation/pnr/reports/power -report_prefix compteur.stat -format detailed
+*
+-----------------------------------------------------------------------------------------
+
+
+Total Power
+-----------------------------------------------------------------------------------------
+Total Internal Power: 0.04981982 6.4300%
+Total Switching Power: 0.72497510 93.5690%
+Total Leakage Power: 0.00000781 0.0010%
+Total Power: 0.77480273
+-----------------------------------------------------------------------------------------
+
+
+Group Internal Switching Leakage Total Percentage
+ Power Power Power Power (%)
+-----------------------------------------------------------------------------------------
+Sequential 0.03148 0.001147 2.442e-06 0.03263 4.212
+Macro 0 0 0 0 0
+IO 0 0 0 0 0
+Combinational 0.01834 0.7238 5.369e-06 0.7422 95.79
+Clock (Combinational) 0 0 0 0 0
+Clock (Sequential) 0 0 0 0 0
+-----------------------------------------------------------------------------------------
+Total 0.04982 0.725 7.811e-06 0.7748 100
+-----------------------------------------------------------------------------------------
+
+
+Rail Voltage Internal Switching Leakage Total Percentage
+ Power Power Power Power (%)
+-----------------------------------------------------------------------------------------
+VDD 1.1 0.04982 0.725 7.811e-06 0.7748 100
+
+
+-----------------------------------------------------------------------------------------
+* Power Distribution Summary:
+* Highest Average Power: FE_OFC14_o_cnt_1 (CLKINVX20): 0.2095
+* Highest Leakage Power: FE_OFC20_o_cnt_0 (BUFX20): 1.034e-06
+* Total Cap: 4.04623e-12 F
+* Total instances in design: 32
+* Total instances in design with no power: 0
+* Total instances in design with no activity: 0
+* Total Fillers and Decap: 0
+-----------------------------------------------------------------------------------------
+
diff --git a/compteur/implementation/pnr/reports/compteur.timing.rpt b/compteur/implementation/pnr/reports/compteur.timing.rpt
index 0f743af3068990782f3165df648ffed4c250dac7..8d9d669cfc242b35da80172062f1c972c1b737d3 100644
--- a/compteur/implementation/pnr/reports/compteur.timing.rpt
+++ b/compteur/implementation/pnr/reports/compteur.timing.rpt
@@ -1,7 +1,7 @@
###############################################################
# Generated by: Cadence Innovus 17.11-s080_1
# OS: Linux x86_64(Host ID pcys41)
-# Generated on: Fri Mar 29 20:17:15 2019
+# Generated on: Tue Sep 10 10:50:10 2019
# Design: compteur
# Command: report_timing > $::env(PNR_REP_DIR)/${DESIGN}.timing.rpt
###############################################################
diff --git a/compteur/implementation/syn/netlist/compteur.syn.sdf b/compteur/implementation/syn/netlist/compteur.syn.sdf
index defa8abaf11b6a389f498eaa4ff063c5da75801a..a45e2c06dcaf8aedd0aaacce64d657319f2662db 100644
--- a/compteur/implementation/syn/netlist/compteur.syn.sdf
+++ b/compteur/implementation/syn/netlist/compteur.syn.sdf
@@ -1,7 +1,7 @@
(DELAYFILE
(SDFVERSION "OVI 3.0")
(DESIGN "compteur")
- (DATE "Sun Mar 31 20:02:09 EDT 2019")
+ (DATE "Tue Sep 10 10:42:42 EDT 2019")
(VENDOR "Cadence, Inc.")
(PROGRAM "Genus(TM) Synthesis Solution")
(VERSION "17.10-p007_1")
diff --git a/compteur/implementation/syn/netlist/compteur.syn.v b/compteur/implementation/syn/netlist/compteur.syn.v
index bb2787357ffc016664293ba72810b1b63ed4f294..af80e8c65e6dc0445895e3c3cfc4fac7ae19e31b 100644
--- a/compteur/implementation/syn/netlist/compteur.syn.v
+++ b/compteur/implementation/syn/netlist/compteur.syn.v
@@ -1,6 +1,6 @@
// Generated by Cadence Genus(TM) Synthesis Solution 17.10-p007_1
-// Generated on: Mar 31 2019 20:02:09 EDT (Apr 1 2019 00:02:09 UTC)
+// Generated on: Sep 10 2019 10:42:42 EDT (Sep 10 2019 14:42:42 UTC)
// Verification Directory fv/compteur
diff --git a/compteur/implementation/syn/reports/compteur.syn.area.rpt b/compteur/implementation/syn/reports/compteur.syn.area.rpt
index 9f6fa650e172d74be5edc9e00f2a98cc0fa793c0..886e7ea1e7899b3bd33b8ff78547706a72fd4f01 100644
--- a/compteur/implementation/syn/reports/compteur.syn.area.rpt
+++ b/compteur/implementation/syn/reports/compteur.syn.area.rpt
@@ -1,6 +1,6 @@
============================================================
Generated by: Genus(TM) Synthesis Solution 17.10-p007_1
- Generated on: Mar 31 2019 08:02:09 pm
+ Generated on: Sep 10 2019 10:42:42 am
Module: compteur
Operating conditions: PVT_1P1V_0C
Interconnect mode: global
diff --git a/compteur/implementation/syn/reports/compteur.syn.gates.rpt b/compteur/implementation/syn/reports/compteur.syn.gates.rpt
index 2f25bb94682c8cead9560875dd89e217fe33d9ed..139084c6876b9f3d121f79f920050ab8c22ae3f2 100644
--- a/compteur/implementation/syn/reports/compteur.syn.gates.rpt
+++ b/compteur/implementation/syn/reports/compteur.syn.gates.rpt
@@ -1,6 +1,6 @@
============================================================
Generated by: Genus(TM) Synthesis Solution 17.10-p007_1
- Generated on: Mar 31 2019 08:02:09 pm
+ Generated on: Sep 10 2019 10:42:42 am
Module: compteur
Operating conditions: PVT_1P1V_0C
Interconnect mode: global
diff --git a/compteur/implementation/syn/reports/compteur.syn.power.rpt b/compteur/implementation/syn/reports/compteur.syn.power.rpt
index 800b2374fc3908894f8c8048e6f8f60763abb47d..89770e44e1d969a252df21631297d3616cce3d32 100644
--- a/compteur/implementation/syn/reports/compteur.syn.power.rpt
+++ b/compteur/implementation/syn/reports/compteur.syn.power.rpt
@@ -1,6 +1,6 @@
============================================================
Generated by: Genus(TM) Synthesis Solution 17.10-p007_1
- Generated on: Mar 31 2019 08:02:09 pm
+ Generated on: Sep 10 2019 10:42:42 am
Module: compteur
Operating conditions: PVT_1P1V_0C
Interconnect mode: global
diff --git a/compteur/implementation/syn/reports/compteur.syn.timing.rpt b/compteur/implementation/syn/reports/compteur.syn.timing.rpt
index 9bfedf5b1398ee31678b254dbb8f2c694e86975b..9756f5cd7c41eeec317cd0ec6dd109ce8c56b3bf 100644
--- a/compteur/implementation/syn/reports/compteur.syn.timing.rpt
+++ b/compteur/implementation/syn/reports/compteur.syn.timing.rpt
@@ -1,6 +1,6 @@
============================================================
Generated by: Genus(TM) Synthesis Solution 17.10-p007_1
- Generated on: Mar 31 2019 08:02:09 pm
+ Generated on: Sep 10 2019 10:42:42 am
Module: compteur
Operating conditions: PVT_1P1V_0C
Interconnect mode: global
diff --git a/compteur/implementation/syn/reports/compteur.syn.timing_lint.rpt b/compteur/implementation/syn/reports/compteur.syn.timing_lint.rpt
index 222040facfaf598f55b56dcc5455ca13ac055e3a..d2e377e11b150d4d84d18afede49ec776626683b 100644
--- a/compteur/implementation/syn/reports/compteur.syn.timing_lint.rpt
+++ b/compteur/implementation/syn/reports/compteur.syn.timing_lint.rpt
@@ -1,6 +1,6 @@
============================================================
Generated by: Genus(TM) Synthesis Solution 17.10-p007_1
- Generated on: Mar 31 2019 08:02:07 pm
+ Generated on: Sep 10 2019 10:42:40 am
Module: compteur
Technology library: fast_vdd1v0 1.0
Operating conditions: PVT_1P1V_0C
diff --git a/compteur/scripts/pnr.tcl b/compteur/scripts/pnr.tcl
index d134861d4edd015a1944cbbc8cbc15655f880a0d..0e3a0ceadb6e8e55c2c8a17205788cd7ec6b4002 100644
--- a/compteur/scripts/pnr.tcl
+++ b/compteur/scripts/pnr.tcl
@@ -1,21 +1,19 @@
#-----------------------------------------------------------------------------
-# Project : ELE8304 : Circuits intégrés à très grande échelle
+# Project : Tutoriels - Conception de circuits intégrés numériques
#-----------------------------------------------------------------------------
# File : pnr.tcl
-# Author : Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
-# Lab : grm@polymtl
-# Created : 2018-06-22
-# Last update: 2019-03-29
+# Authors : Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
+# Lab : GRM - Polytechnique Montréal
+# Date : <2019-07-24 Wed>
#-----------------------------------------------------------------------------
# Description: Placement et routage du compteur BCD avec Innovus
# HOW-TO : source setup.csh && cd implementation/pnr && innovus
-# : innovus> source ${SCRIPTS_DIR}/pnr.tcl
+# : innovus -files ${SCRIPTS_DIR}/pnr.tcl
#-----------------------------------------------------------------------------
-#-----------------------------------------------------------------------------#
-# FLOW CONTROL #
-#-----------------------------------------------------------------------------#
-
+#-----------------------------------------------------------------------------
+# CONFIG
+#-----------------------------------------------------------------------------
set DO_INIT 1
set DO_FP 1
set DO_POWER 1
@@ -26,12 +24,11 @@ set DO_ROUTE 1
set DO_CHECK 1
set DO_SAVE 1
-#-----------------------------------------------------------------------------#
-# SETUP #
-#-----------------------------------------------------------------------------#
-
set DESIGN compteur
+#-----------------------------------------------------------------------------
+# INIT
+#-----------------------------------------------------------------------------
if { $DO_INIT } {
set init_oa_ref_lib [list gsclib045_tech gsclib045 giolib045]
@@ -43,19 +40,19 @@ if { $DO_INIT } {
set init_pwr_net VDD
init_design
-}
+}
-#-----------------------------------------------------------------------------#
-# FLOORPLAN #
-#-----------------------------------------------------------------------------#
+#-----------------------------------------------------------------------------
+# FLOORPLAN
+#-----------------------------------------------------------------------------
if { $DO_FP } {
floorPlan -site CoreSite -r 0.9 0.6 1 1 1 1
}
-#-----------------------------------------------------------------------------#
-# POWER #
-#-----------------------------------------------------------------------------#
+#-----------------------------------------------------------------------------
+# ALIMENTATIONS
+#-----------------------------------------------------------------------------
if { $DO_POWER } {
globalNetConnect VDD -type pgpin -pin VDD -inst * -override
@@ -84,9 +81,9 @@ if { $DO_POWER } {
-layerChangeRange { Metal1(1) Metal1(1) }
}
-#-----------------------------------------------------------------------------#
-# I/O #
-#-----------------------------------------------------------------------------#
+#-----------------------------------------------------------------------------
+# I/O
+#-----------------------------------------------------------------------------
if { $DO_IO } {
# Nets
@@ -115,9 +112,9 @@ if { $DO_IO } {
-start 1 0 -end 11 0
}
-#-----------------------------------------------------------------------------#
-# PLACE #
-#-----------------------------------------------------------------------------#
+#-----------------------------------------------------------------------------
+# PLACEMENT
+#-----------------------------------------------------------------------------
if { $DO_PLACE } {
setDesignMode -process 45
@@ -126,9 +123,9 @@ if { $DO_PLACE } {
placeDesign
}
-#-----------------------------------------------------------------------------#
-# CTS #
-#-----------------------------------------------------------------------------#
+#-----------------------------------------------------------------------------
+# ARBRE D'HORLOGE
+#-----------------------------------------------------------------------------
if { $DO_CTS } {
optDesign -preCTS -outDir $::env(PNR_REP_DIR)/cts
@@ -176,9 +173,9 @@ if { $DO_CHECK } {
report_timing > $::env(PNR_REP_DIR)/${DESIGN}.timing.rpt
}
-#-----------------------------------------------------------------------------#
-# REPORTS #
-#-----------------------------------------------------------------------------#
+#-----------------------------------------------------------------------------
+# SAUVEGARDES
+#-----------------------------------------------------------------------------
if { $DO_SAVE } {
if {! [file isdirectory $::env(PNR_OA_LIB)] } {
diff --git a/compteur/scripts/pwr.tcl b/compteur/scripts/pwr.tcl
index 8506b5f6e093b2b172d20f5c3ccf949cf7d37c34..d56452f24a46dc6dfb90c3937d516efd5cc7d585 100644
--- a/compteur/scripts/pwr.tcl
+++ b/compteur/scripts/pwr.tcl
@@ -1,32 +1,30 @@
#-----------------------------------------------------------------------------
-# Project : ELE8304 : Circuits intégrés à très grande échelle
+# Project : Tutoriels - Conception de circuits intégrés numériques
#-----------------------------------------------------------------------------
# File : pwr.tcl
-# Author : Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
-# Lab : grm@polymtl
-# Created : 2018-06-22
-# Last update: 2019-03-29
+# Authors : Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
+# Lab : GRM - Polytechnique Montréal
+# Date : <2019-07-24 Wed>
#-----------------------------------------------------------------------------
# Description: Estimation du puissance du compteur BCD avec Voltus
# HOW-TO : source setup.csh && cd implementation/pnr
# : > voltus -files ${SCRIPTS_DIR}/pwr.tcl
#-----------------------------------------------------------------------------
-#----------------------------------------------------------------------------#
-# SETUP #
-#----------------------------------------------------------------------------#
-set DESIGN compteur
-
+#-----------------------------------------------------------------------------
+# CONFIG
+#-----------------------------------------------------------------------------
set DO_INIT 1
set DO_STAT 0
set DO_DYN 1
-set VCD_START "0"
-set VCD_END "39"
+set DESIGN compteur
+set VCD_START 0
+set VCD_END 39
-#----------------------------------------------------------------------------#
-# INIT #
-#----------------------------------------------------------------------------#
+#-----------------------------------------------------------------------------
+# INIT
+#-----------------------------------------------------------------------------
if { $DO_INIT } {
read_design -cellview "$::env(PNR_OA_LIB) $DESIGN layout" -physical_data
@@ -39,11 +37,13 @@ if { $DO_INIT } {
generate_pg_library -output $::env(PNR_REP_DIR)/power
}
-#----------------------------------------------------------------------------#
-# STATIC POWER #
-#----------------------------------------------------------------------------#
+#-----------------------------------------------------------------------------
+# ANALYSE STATIQUE
+#-----------------------------------------------------------------------------
if { $DO_STAT } {
+ set rep ${DESIGN}.stat
+
# Static mode
set_power_analysis_mode -reset
set_power_analysis_mode -method static \
@@ -56,17 +56,16 @@ if { $DO_STAT } {
# Activity
set_default_switching_activity -reset
- set_default_switching_activity -input_activity 0.2 -period 1.0
-
- # Report Power
- report_power -format detailed -report_prefix ${DESIGN}.stat -output $::env(PNR_REP_DIR)/power
+ set_default_switching_activity -input_activity 0.2 -period 1.0
}
-#----------------------------------------------------------------------------#
-# DYNAMIC POWER #
-#----------------------------------------------------------------------------#
+#-----------------------------------------------------------------------------
+# ANALYSE DYNAMIQUE
+#-----------------------------------------------------------------------------
if { $DO_DYN } {
+ set rep ${DESIGN}.dyn
+
# Reset mode
set_power_analysis_mode -reset
set_default_switching_activity -reset
@@ -85,8 +84,9 @@ if { $DO_DYN } {
# Read VCD activity file
read_activity_file -reset
read_activity_file -format VCD $::env(SIM_PNR_DIR)/${DESIGN}.pnr.vcd \
- -scope ${DESIGN}_tb/dut -start $VCD_START -end $VCD_END
-
- # Report power
- report_power -format detailed -report_prefix ${DESIGN}.dyn -output $::env(PNR_REP_DIR)/power
+ -scope ${DESIGN}_tb/dut -start $VCD_START -end $VCD_END
}
+
+# Report power
+report_power -format detailed -report_prefix $rep -output $::env(PNR_REP_DIR)/power
+file copy -force $::env(PNR_REP_DIR)/power/${rep}.rpt $::env(PNR_REP_DIR)/${rep}.rpt
diff --git a/compteur/scripts/sim.tcl b/compteur/scripts/sim.tcl
index 6cb568045d2844fc7dc492bd1a4e8404cd025df1..54dfe2fff115743faae3cd0527a07c65bb56dc7e 100644
--- a/compteur/scripts/sim.tcl
+++ b/compteur/scripts/sim.tcl
@@ -1,11 +1,10 @@
#-----------------------------------------------------------------------------
-# Project : ELE8304 : Circuits intégrés à très grande échelle
+# Project : Tutoriels - Conception de circuits intégrés numériques
#-----------------------------------------------------------------------------
# File : sim.tcl
-# Author : Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
-# Lab : grm@polymtl
-# Created : 2018-06-22
-# Last update: 2019-03-29
+# Authors : Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
+# Lab : GRM - Polytechnique Montréal
+# Date : <2019-07-24 Wed>
#-----------------------------------------------------------------------------
# Description: Script pour les simulations du compteur BCD avec Modelsim
# HOW-TO : source setup.csh && cd simulation/
@@ -16,12 +15,12 @@
#-----------------------------------------------------------------------------
# CONFIG
#-----------------------------------------------------------------------------
-set DO_BEH 0; # Simulation du modèle comportemental
+set DO_BEH 1; # Simulation du modèle comportemental
set DO_SYN 0; # Smulation de la netlist post-synthèse
-set DO_PNR 1; # Simulation de la netlist post-implémentation
-set DO_RUN 1; # 0=Compilation; 1=Compilation + Simulation
+set DO_PNR 0; # Simulation de la netlist post-implémentation
+set DO_RUN 0; # 0=Compilation; 1=Compilation + Simulation
set DO_WAVE 0; # Chargement des chronogrammes
-set DO_VCD 1; # Enregistrement de l'activité dans un fichier vcd
+set DO_VCD 0; # Enregistrement de l'activité dans un fichier vcd
#-----------------------------------------------------------------------------
# DEFAULTS
diff --git a/compteur/scripts/syn.tcl b/compteur/scripts/syn.tcl
index af198f1465f210f5f163e45b0d527df7a4cac154..9e742acddb439f4ab69a1d3a193121a2b82f457c 100644
--- a/compteur/scripts/syn.tcl
+++ b/compteur/scripts/syn.tcl
@@ -1,35 +1,31 @@
#-----------------------------------------------------------------------------
-# Project : ELE8304 : Circuits intégrés à très grande échelle
+# Project : Tutoriels - Conception de circuits intégrés numériques
#-----------------------------------------------------------------------------
# File : syn.tcl
-# Author : Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
-# Lab : grm@polymtl
-# Created : 2018-06-22
-# Last update: 2019-03-29
+# Authors : Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
+# Lab : GRM - Polytechnique Montréal
+# Date : <2019-07-24 Wed>
#-----------------------------------------------------------------------------
# Description: Script pour la synthèse du compteur BCD avec Genus
# HOW-TO : > source setup.csh && cd implementation/syn
# : > genus -files ${SCRIPTS_DIR}/syn.tcl
#-----------------------------------------------------------------------------
-#----------------------------------------------------------------------------#
-# SETUP #
-#----------------------------------------------------------------------------#
-
-set DESIGN compteur
-
+#-----------------------------------------------------------------------------
+# CONFIG
+#-----------------------------------------------------------------------------
set DO_INIT 1
set DO_ELAB 1
set DO_SDC 1
set DO_SYN 1
set DO_REPORTS 1
-set SYN_EFFORT high; # low | medium | high | express
-
-#----------------------------------------------------------------------------#
-# INIT #
-#----------------------------------------------------------------------------#
+set DESIGN compteur
+set SYN_EFFORT high; # low | medium | high | express
+#-----------------------------------------------------------------------------
+# INIT
+#-----------------------------------------------------------------------------
if { $DO_INIT } {
# Paramètres de base
@@ -53,11 +49,10 @@ if { $DO_INIT } {
set_db / .interconnect_mode ple; # wireload ou ple (Physical Layout Estimators)
}
-#----------------------------------------------------------------------------#
-# ELABORATION #
-#----------------------------------------------------------------------------#
-
-set sources "compteur.vhd"
+#-----------------------------------------------------------------------------
+# ELABORATION
+#-----------------------------------------------------------------------------
+set sources [list compteur.vhd]
if { $DO_ELAB } {
@@ -77,9 +72,9 @@ if { $DO_ELAB } {
check_design -all
}
-#----------------------------------------------------------------------------#
-# CONTRAINTES #
-#----------------------------------------------------------------------------#
+#-----------------------------------------------------------------------------
+# CONTRAINTES
+#-----------------------------------------------------------------------------
if { $DO_SDC } {
# Contraintes de timing
@@ -89,10 +84,9 @@ if { $DO_SDC } {
report_timing -lint > $::env(SYN_REP_DIR)/${DESIGN}.syn.timing_lint.rpt
}
-#----------------------------------------------------------------------------#
-# SYNTHESE #
-#----------------------------------------------------------------------------#
-
+#-----------------------------------------------------------------------------
+# SYNTHESE
+#-----------------------------------------------------------------------------
if { $DO_SYN } {
# Ungroup
@@ -111,10 +105,9 @@ if { $DO_SYN } {
syn_opt $DESIGN
}
-#----------------------------------------------------------------------------#
-# RAPPORTS & NETLIST #
-#----------------------------------------------------------------------------#
-
+#-----------------------------------------------------------------------------
+# RAPPORTS & NETLIST
+#-----------------------------------------------------------------------------
if { $DO_REPORTS } {
# Rapports
diff --git a/compteur/setup.csh b/compteur/setup.csh
index 62800805f5b80a82c8c2b132cde4b347ee085f12..58e7155a99a72d5d5ce2eb291ed4b1c25a003709 100644
--- a/compteur/setup.csh
+++ b/compteur/setup.csh
@@ -17,7 +17,6 @@
#-----------------------------------------------------------------------------
# CONFIGURATION
#-----------------------------------------------------------------------------
-
setenv CMC_CONFIG "/CMC/scripts/cmc.2017.12.csh"
setenv PROJECT_HOME `pwd`
@@ -38,27 +37,19 @@ source ${CMC_CONFIG}
#-----------------------------------------------------------------------------
# HIERARCHIE DU PROJET
#-----------------------------------------------------------------------------
-
-# Global
setenv SRC_DIR ${PROJECT_HOME}/sources
setenv CONST_DIR ${PROJECT_HOME}/constraints
setenv SIM_DIR ${PROJECT_HOME}/simulation
setenv IMP_DIR ${PROJECT_HOME}/implementation
setenv DOC_DIR ${PROJECT_HOME}/../doc
setenv SCRIPTS_DIR ${PROJECT_HOME}/scripts
-
-# Simulations
setenv SIM_BEH_DIR ${SIM_DIR}/beh
setenv SIM_SYN_DIR ${SIM_DIR}/syn
setenv SIM_PNR_DIR ${SIM_DIR}/pnr
-
-# Synthesis
setenv SYN_DIR ${IMP_DIR}/syn
setenv SYN_NET_DIR ${SYN_DIR}/netlist
setenv SYN_REP_DIR ${SYN_DIR}/reports
setenv SYN_LOG_DIR ${SYN_DIR}/logs
-
-# Place and Route
setenv PNR_DIR ${IMP_DIR}/pnr
setenv PNR_NET_DIR ${PNR_DIR}/netlist
setenv PNR_REP_DIR ${PNR_DIR}/reports
@@ -67,8 +58,10 @@ setenv PNR_OA_LIB liboa
#-----------------------------------------------------------------------------
# CONFIGURATION DU KIT GPDK045
#-----------------------------------------------------------------------------
-
-setenv KIT_HOME ${CMC_HOME}/kits/GPDK45
+setenv KIT_HOME ${CMC_HOME}/kits/GPDK45
+setenv KIT_SCLIB ${KIT_HOME}/gsclib045
+setenv KIT_IOLIB ${KIT_HOME}/giolib045
+setenv KIT_GPDK ${KIT_HOME}/gpdk045
# Librairies Modelsim
setenv SIMLIB ${KIT_HOME}/simlib
@@ -76,13 +69,13 @@ setenv SIMLIB_VHD fast_vdd1v0_basicCells
setenv SIMLIB_VER gpdk45
# Front-End
-setenv FE_DIR ${KIT_HOME}/tech/gsclib045/gsclib045
+setenv FE_DIR ${KIT_SCLIB}/gsclib045
setenv FE_VER_LIB ${FE_DIR}/verilog
setenv FE_VHD_LIB ${FE_DIR}/vhdl
setenv FE_TIM_LIB ${FE_DIR}/timing
# Back-End
-setenv BE_DIR ${KIT_HOME}/tech/gsclib045/gsclib045
+setenv BE_DIR ${KIT_SCLIB}/gsclib045
setenv BE_LEF_LIB ${BE_DIR}/lef
setenv BE_CDB_LIB ${BE_DIR}/celtic
setenv BE_OA_LIB ${BE_DIR}/oa22/gsclib045
@@ -91,7 +84,7 @@ setenv BE_GDS_LIB ${BE_DIR}/gds
setenv BE_SPICE_LIB ${BE_DIR}/spectre/gsclib045
# I/O
-setenv IO_DIR ${KIT_HOME}/tech/giolib045/giolib045
+setenv IO_DIR ${KIT_IOLIB}/giolib045
setenv IO_VHDL_LIB ${IO_DIR}/vhdl
setenv IO_VER_LIB ${IO_DIR}/vlog
setenv IO_LEF_LIB ${IO_DIR}/lef
@@ -111,6 +104,9 @@ alias vsim_help "${MGC_HTML_BROWSER} ${CMC_MNT_MSIM_HOME}/docs/index.html"
# CADENCE
source ${CMC_HOME}/scripts/cadence.2014.12.csh
+if ( ! -e /export/tmp/$user ) then
+ mkdir -p /export/tmp/$user
+endif
setenv DRCTEMPDIR /export/tmp/$user
# GENUS
diff --git a/compteur/simulation/.gitignore b/compteur/simulation/.gitignore
index 3fa4b63a472dd0e8a68cf5976ae59462d32fd531..e63c85ec84980c61e8931bd365698dc81c8e76af 100644
--- a/compteur/simulation/.gitignore
+++ b/compteur/simulation/.gitignore
@@ -3,4 +3,5 @@ beh/work/
syn/work/
pnr/work/
transcript
-vsim.wlf
\ No newline at end of file
+vsim.wlf
+*.vcd
diff --git a/compteur/simulation/beh/compteur.beh.vcd b/compteur/simulation/beh/compteur.beh.vcd
deleted file mode 100644
index bd5b1c572705550ec3dc779de9f1752ac0ab3935..0000000000000000000000000000000000000000
--- a/compteur/simulation/beh/compteur.beh.vcd
+++ /dev/null
@@ -1,168 +0,0 @@
-$date
- Sat Mar 30 12:49:41 2019
-$end
-$version
- ModelSim Version 10.7a
-$end
-$timescale
- 1ps
-$end
-
-$scope module compteur_tb $end
-
-$scope module dut $end
-$var wire 1 ! o_cnt [3] $end
-$var wire 1 " o_cnt [2] $end
-$var wire 1 # o_cnt [1] $end
-$var wire 1 $ o_cnt [0] $end
-$var wire 1 % cnt [3] $end
-$var wire 1 & cnt [2] $end
-$var wire 1 ' cnt [1] $end
-$var wire 1 ( cnt [0] $end
-$var wire 1 ) rstn_sync [1] $end
-$var wire 1 * rstn_sync [0] $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-#0
-$dumpvars
-0)
-0*
-0!
-0"
-0#
-0$
-0%
-0&
-0'
-0(
-$end
-#2500
-1*
-#3500
-1)
-#4500
-1(
-1$
-#5500
-0(
-1'
-0$
-1#
-#6500
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-#7500
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-#10500
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-#11500
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-0*
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-0#
-#22500
-1*
-#23500
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-#25500
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-1'
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-1#
-#26500
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-1$
-#27500
-0(
-0'
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-0$
-0#
-1"
-#28500
-1(
-1$
-#29500
-0(
-1'
-0$
-1#
-#30500
-1(
-1$
-#31500
-0(
-0'
-0&
-1%
-0$
-0#
-0"
-1!
-#32500
-1(
-1$
-#33500
-0(
-0%
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-1$
diff --git a/compteur/simulation/pnr/compteur.pnr.vcd b/compteur/simulation/pnr/compteur.pnr.vcd
deleted file mode 100644
index d7815cc043a1b9586688a2548a318960e23a497a..0000000000000000000000000000000000000000
--- a/compteur/simulation/pnr/compteur.pnr.vcd
+++ /dev/null
@@ -1,978 +0,0 @@
-$date
- Mon Apr 1 09:18:00 2019
-$end
-$version
- ModelSim Version 10.7a
-$end
-$timescale
- 1ps
-$end
-
-$scope module compteur_tb $end
-
-$scope module dut $end
-$var wire 1 ! i_clk $end
-$var wire 1 " i_rstn $end
-$var wire 1 # i_en $end
-$var wire 1 $ o_cnt [3] $end
-$var wire 1 % o_cnt [2] $end
-$var wire 1 & o_cnt [1] $end
-$var wire 1 ' o_cnt [0] $end
-$var wire 1 ( FE_OFN19_o_cnt_0 $end
-$var wire 1 ) FE_OFN17_o_cnt_3 $end
-$var wire 1 * FE_OFN16_o_cnt_0 $end
-$var wire 1 + FE_OFN15_o_cnt_0 $end
-$var wire 1 , FE_OFN14_o_cnt_1 $end
-$var wire 1 - FE_OFN13_o_cnt_1 $end
-$var wire 1 . FE_OFN12_o_cnt_2 $end
-$var wire 1 / FE_OFN11_o_cnt_2 $end
-$var wire 1 0 FE_OFN10_o_cnt_3 $end
-$var wire 1 1 FE_OFN9_o_cnt_3 $end
-$var wire 1 2 FE_OFN8_o_cnt_0 $end
-$var wire 1 3 FE_OFN7_o_cnt_0 $end
-$var wire 1 4 FE_OFN6_o_cnt_1 $end
-$var wire 1 5 FE_OFN5_o_cnt_1 $end
-$var wire 1 6 FE_OFN4_o_cnt_2 $end
-$var wire 1 7 FE_OFN3_o_cnt_2 $end
-$var wire 1 8 FE_OFN1_o_cnt_3 $end
-$var wire 1 9 FE_OFN0_o_cnt_3 $end
-$var wire 1 : rstn_sync [1] $end
-$var wire 1 ; rstn_sync [0] $end
-$var wire 1 < n_8 $end
-$var wire 1 = n_9 $end
-$var wire 1 > n_11 $end
-$var wire 1 ? n_12 $end
-$var wire 1 @ n_13 $end
-$var wire 1 A n_16 $end
-$var wire 1 B n_17 $end
-$var wire 1 C n_18 $end
-$var wire 1 D n_19 $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-#0
-$dumpvars
-x(
-x)
-x*
-x+
-x,
-x-
-x.
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-x0
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-x?
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-0!
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-$end
-#20
-0;
-0@
-#30
-1?
-1B
-0:
-#60
-03
-07
-09
-#70
-05
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diff --git a/compteur/simulation/syn/compteur.syn.vcd b/compteur/simulation/syn/compteur.syn.vcd
deleted file mode 100644
index c27ecfffbd0f47f63bfad1ecc5e01ec97d4dffa6..0000000000000000000000000000000000000000
--- a/compteur/simulation/syn/compteur.syn.vcd
+++ /dev/null
@@ -1,686 +0,0 @@
-$date
- Sat Mar 30 12:57:51 2019
-$end
-$version
- ModelSim Version 10.7a
-$end
-$timescale
- 1ps
-$end
-
-$scope module compteur_tb $end
-
-$scope module dut $end
-$var wire 1 ! i_clk $end
-$var wire 1 " i_rstn $end
-$var wire 1 # i_en $end
-$var wire 1 $ o_cnt [3] $end
-$var wire 1 % o_cnt [2] $end
-$var wire 1 & o_cnt [1] $end
-$var wire 1 ' o_cnt [0] $end
-$var wire 1 ( rstn_sync [1] $end
-$var wire 1 ) rstn_sync [0] $end
-$var wire 1 * cnt [3] $end
-$var wire 1 + cnt [2] $end
-$var wire 1 , cnt [1] $end
-$var wire 1 - cnt [0] $end
-$var wire 1 . n_1 $end
-$var wire 1 / n_3 $end
-$var wire 1 0 n_8 $end
-$var wire 1 1 n_9 $end
-$var wire 1 2 n_11 $end
-$var wire 1 3 n_12 $end
-$var wire 1 4 n_13 $end
-$var wire 1 5 n_16 $end
-$var wire 1 6 n_17 $end
-$var wire 1 7 n_18 $end
-$var wire 1 8 n_19 $end
-$upscope $end
-$upscope $end
-$enddefinitions $end
-#0
-$dumpvars
-x)
-x(
-x-
-x,
-x+
-x*
-x.
-x/
-x0
-x1
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-$end
-#20
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diff --git a/compteur/sources/compteur.vhd b/compteur/sources/compteur.vhd
index 136081fd89c0aa4b7f2af4384bd9635afd5de56f..c7e93d77f58149d5a47d477f3c7a0905891c51c6 100644
--- a/compteur/sources/compteur.vhd
+++ b/compteur/sources/compteur.vhd
@@ -1,11 +1,10 @@
-------------------------------------------------------------------------------
--- Project : ELE8304 : Circuits intégrés à très grande échelle
+-- Project : Tutoriels - Conception de circuits intégrés numériques
-------------------------------------------------------------------------------
-- File : compteur.vhd
-- Author : Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
-- Lab : grm@polymtl
--- Created : 2018-06-22
--- Last update: 2019-03-29
+-- Date : 2019-07-24
-------------------------------------------------------------------------------
-- Description: Compteur BCD Ã 1 chiffre (4 bits)
-------------------------------------------------------------------------------
@@ -35,7 +34,7 @@ begin
o_cnt <= std_logic_vector(cnt);
-- Reset synchronizer
- P_rstn: process (i_clk)
+ p_rstn: process (i_clk)
begin
if (i_rstn = '0') then
rstn_sync <= (others => '0');
@@ -43,10 +42,10 @@ begin
rstn_sync(0) <= '1';
rstn_sync(1) <= rstn_sync(0);
end if;
- end process P_rstn;
+ end process p_rstn;
-- Main process with asynchronous reset
- P_bcd: process (i_clk, rstn)
+ p_bcd: process (i_clk, rstn)
begin
if (rstn = '0') then
cnt <= (others => '0');
@@ -59,6 +58,6 @@ begin
end if;
end if;
end if;
- end process P_bcd;
+ end process p_bcd;
end architecture beh;
diff --git a/compteur/sources/compteur_tb.vhd b/compteur/sources/compteur_tb.vhd
index e8af25e4e1daeb3a1e708bb31505746c7214501f..bb9f4d5b675fc842a805484ee74b8b234564e3eb 100644
--- a/compteur/sources/compteur_tb.vhd
+++ b/compteur/sources/compteur_tb.vhd
@@ -1,11 +1,10 @@
-------------------------------------------------------------------------------
--- Project : ELE8304 : Circuits intégrés à très grande échelle
+-- Project : Tutoriels - Conception de circuits intégrés numériques
-------------------------------------------------------------------------------
-- File : compteur_tb.vhd
-- Author : Mickael Fiorentino <mickael.fiorentino@polymtl.ca>
-- Lab : grm@polymtl
--- Created : 2018-06-22
--- Last update: 2019-03-29
+-- Date : 2019-07-24
-------------------------------------------------------------------------------
-- Description: Banc d'essai du compteur BCD
-------------------------------------------------------------------------------
@@ -56,9 +55,9 @@ begin
o_cnt => cnt);
-- Main TB process
- P_tb : process
+ p_main : process
begin
- report "*** Simulation Starts ***";
+ report "SIMULATION STARTS";
for i in 0 to TB_LOOP-1 loop
en <= '0';
@@ -66,7 +65,7 @@ begin
wait for 2.3 * PERIOD;
rst_n <= '1';
en <= '1';
- wait for 15*PERIOD;
+ wait for 15 * PERIOD;
en <= '0';
-- Assertion
@@ -78,8 +77,8 @@ begin
end loop;
- report "*** Simulation Ends ***";
+ report "SIMULATION ENDS";
stop;
- end process P_tb;
+ end process p_main;
end architecture tb;