Importation des fichiers

README.md

+# Tutoriels - Conception de circuits intégrés analogiques
+---
+
+Ce répertoire contient les sources associées aux guides d'utilisation des outils de conception de circuits intégrés analogiques disponibles dans les laboratoires [GRM](https://www.gr2m.polymtl.ca/) et [VLSI](https://www.vlsi.polymtl.ca/) de Polytechnique Montréal.
+
+Les tutoriels sont hébergés sur le [Wiki du GRM](https://intranet.grm.polymtl.ca/wiki/). Ils s'adressent aux checheurs du GRM ainsi qu'aux étudiants des cours [ELE6308](https://www.polymtl.ca/etudes/cours/microelectronique-analogique-et-mixte), et [GBM8320](https://www.polymtl.ca/etudes/cours/dispositifs-medicaux-intelligents).
+
+Les logiciels et les technologies utilisées sont fournis par [[https://www.cmc.ca][CMC]]. Le kit de référence est basé sur la technologie 45nm éducative de *Cadence*: *Generic Process Design Kit* [GPDK045](https://www.cmc.ca/WhatWeOffer/Products/CMC-00200-04870.aspx).
+

inverseur/.cdsenv

+;              Cadence environment variable file (.cdsenv)
+;
+;	samples values can be found in:
+;		/CMC/tools/cadence/IC617_lnx86/tools/dfII/samples/.cdsenv
+;
+;---------------------------------------------------------------------------
+
+;;;;;;;;;;;;;;
+;; ADE setup
+;;;;;;;;;;;;;;
+asimenv.startup       projectDir       string  "/export/tmp/8304_1/simulations"
+asimenv.startup       simulator        string  "spectre"
+asimenv               saveAsCellview   boolean t
+
+;;;;;;;;;;;;;;
+;; CIW options
+;;;;;;;;;;;;;;
+ui	showScrollBars	boolean	t
+
+;;;;;;;;;;;;;;
+;; turn off Whats New displays
+;;;;;;;;;;;;;;
+ddserv	showWhatsNew	string	"no"
+
+;;;;;;;;;;;;;;
+;; Use next license available
+;;;;;;;;;;;;;;
+license	VLSL_UseNextLicense	string	"always"
+license	ADEL_UseNextLicense	string	"always"
+license	VSEL_UseNextLicense	string	"always"

inverseur/.cdsinit

+;               Cadence Initialization File (.cdsinit)
+;		
+;
+;	defaults values/examples can be found in:
+;		/CMC/tools/cadence/IC617_lnx86/tools/dfII/samples/local/cdsinit
+;		/CMC/tools/cadence/IC617_lnx86/tools/dfII/cdsuser/.cdsinit
+;
+;---------------------------------------------------------------------------
+
+;; Load Cadence environment file, alternative way:
+;      when( isFile("./.cdsenv") 
+;            printf("\nFYI: Load the local ./.cdsenv file.")
+;            envLoadFile(".cdsenv")
+;            )
+
+;; Automatically launch Library Manager after the CIW appearance:
+;       when( isFile("./cds.lib")
+;             printf("\nFYI: Launched library manager.")
+;             ddsOpenLibManager()
+; 	    )
+
+;; Personal perferences:
+      editor = "gedit"
+;-------------------- End of File --------------------------------------------

inverseur/cds.lib

+#
+# cds.lib par defaut pour le tuto inverseur
+#
+DEFINE analogLib      $CDSHOME/tools/dfII/etc/cdslib/artist/analogLib
+DEFINE basic          $CDSHOME/tools/dfII/etc/cdslib/basic
+DEFINE gpdk045        $LIB_TECHDIR/gpdk045/gpdk045
+DEFINE gsclib045_tech $LIB_TECHDIR/gsclib045/gsclib045_tech/oa22/gsclib045_tech
+DEFINE ele8304        $TUTO_INV/ele8304

inverseur/ele8304/.oalib

+<?xml version="1.0"?>
+
+<Library DMSystem="oaDMFileSys">
+    <oaDMFileSys libReadOnly="No"
+                 origFileSystem="Unix"/>
+</Library>

inverseur/ele8304/INV/av_extracted/CCLFile

+#
+# OPTION COMMAND FILE created by Cadence Quantus QRC Extraction Version 17.2.1-s063 from CCL
+#
+capacitance \
+	 -decoupling_factor 1.0 \
+	 -ground_net "vss"
+distributed_processing \
+	 -multi_cpu 1
+extract \
+	 -selection "all" \
+	 -type "rc_coupled"
+extraction_setup \
+	 -array_vias_spacing auto \
+	 -max_fracture_length infinite \
+	 -max_fracture_length_unit "MICRONS" \
+	 -max_via_array_size \
+		"auto" \
+	 -net_name_space "SCHEMATIC"
+filter_cap \
+	 -exclude_self_cap true
+filter_coupling_cap \
+	 -coupling_cap_threshold_absolute 0.01 \
+	 -coupling_cap_threshold_relative 0.001
+filter_res \
+	 -merge_parallel_res false \
+	 -min_res 0.001
+input_db -type pvs \
+	 -design_cell_name "INV layout ele8304" \
+	 -directory_name "/export/tmp/8304_id-group/verifications/lvs/svdb" \
+	 -format "DFII" \
+	 -run_name "INV"
+log_file \
+	 -file_name "/export/tmp/8304_id-group/verifications/lvs/svdb/qrc.INV.log"
+output_db -type extracted_view \
+	 -cap_component "pcapacitor" \
+	 -cap_property_name "c" \
+	 -cdl_out_map_directory \
+		"/export/tmp/8304_id-group/verifications/lvs" \
+	 -device_finger_delimiter "@" \
+	 -enable_cellview_check true \
+	 -include_cap_model "false" \
+	 -include_parasitic_cap_model "false" \
+	 -include_parasitic_res_model "false" \
+	 -include_res_model "false" \
+	 -res_component "presistor" \
+	 -res_property_name "r" \
+	 -view_name "av_extracted"
+output_setup \
+	 -directory_name "/tmp/qrc_18979" \
+	 -temporary_directory_name "INV"
+process_technology \
+	 -technology_corner \
+		"rcx_typical" \
+	 -technology_library_file "/users/jolico/Projects/tutogrm/Tuto/inverseur/pvs/gpdk045_pvtech.lib" \
+	 -technology_name "gpdk045" \
+	 -temperature \
+		25.0
+
+

inverseur/ele8304/INV/av_extracted/master.tag

+-- Master.tag File, Rev:1.0
+layout.oa

inverseur/ele8304/INV/layout/master.tag

+-- Master.tag File, Rev:1.0
+layout.oa

inverseur/ele8304/INV/schematic/master.tag

+-- Master.tag File, Rev:1.0
+sch.oa

inverseur/ele8304/INV/schematic/sch.oa.cdslck.RHEL30.pcys38.grm.polymtl.ca.21936

+#
+# Edit Lock-Stake file. CAUTION: Please do not change.
+#
+# Information about current Edit Lock Owner.
+#
+LockStakeVersion               1.1
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+HostName                       pcys38.grm.polymtl.ca
+ProcessIdentifier              21936
+ProcessCreationTime_UTC        1535395036
+ProcessCreationTime_Readable   Mon Aug 27 14:37:16 2018 EDT
+AppIdentifier                  OA File System Design Manager
+OSType                         unix
+ReasonForPlacingEditLock       OpenAccess edit lock
+FilePathUsedToEditLock         /users/jolico/Projects/tutogrm/Tuto/inverseur/ele8304/INV/schematic/sch.oa.cdslck
+TimeEditLocked                 Mon Aug 27 22:38:16 2018 EDT