diff --git a/Carte.PcbDoc b/Carte.PcbDoc
index f631846da22a1954073829ec242124e23a6b7a79..4773180581deb14460dc08f185e2b76f57062231 100644
Binary files a/Carte.PcbDoc and b/Carte.PcbDoc differ
diff --git a/Project Outputs for Testeur_de_cable/Design Rule Check - Carte.drc b/Project Outputs for Testeur_de_cable/Design Rule Check - Carte.drc
index ca309fd57380531deda3e203909178af5612a442..d121c3ba972084f48ff7079c7daf660bee776e40 100644
--- a/Project Outputs for Testeur_de_cable/Design Rule Check - Carte.drc	
+++ b/Project Outputs for Testeur_de_cable/Design Rule Check - Carte.drc	
@@ -1,7 +1,7 @@
 Protel Design System Design Rule Check
 PCB File : C:\Users\Yann Roberge\Documents\Ingé\A2019\Testeur de câble\PCB_Project\Carte.PcbDoc
-Date     : 31/12/2019
-Time     : 19:50:44
+Date     : 01/01/2020
+Time     : 01:15:59
 
 Processing Rule : Clearance Constraint (Gap=0.152mm) (All),(All)
 Rule Violations :0
@@ -18,10 +18,10 @@ Rule Violations :0
 Processing Rule : Width Constraint (Min=0.2mm) (Max=0.5mm) (Preferred=0.254mm) (OnLayer('Top Layer'))
 Rule Violations :0
 
-Processing Rule : Width Constraint (Min=0.1mm) (Max=0.4mm) (Preferred=0.254mm) (OnLayer('Top Overlay'))
+Processing Rule : Width Constraint (Min=0.2mm) (Max=0.5mm) (Preferred=0.254mm) (OnLayer('Bottom Layer'))
 Rule Violations :0
 
-Processing Rule : Width Constraint (Min=0.2mm) (Max=0.5mm) (Preferred=0.254mm) (OnLayer('Bottom Layer'))
+Processing Rule : Width Constraint (Min=0.1mm) (Max=0.4mm) (Preferred=0.254mm) (OnLayer('Top Overlay'))
 Rule Violations :0
 
 Processing Rule : Width Constraint (Min=0.1mm) (Max=0.4mm) (Preferred=0.254mm) (OnLayer('Bottom Overlay'))
@@ -51,18 +51,18 @@ Rule Violations :0
 Processing Rule : Net Antennae (Tolerance=0mm) (All)
 Rule Violations :0
 
-Processing Rule : Board Clearance Constraint (Gap=0mm) (OnLayer('Top Overlay'))
-Rule Violations :0
-
 Processing Rule : Board Clearance Constraint (Gap=0mm) (All)
 Rule Violations :0
 
-Processing Rule : Room 7SA (Bounding Region = (79.65mm, 123.1mm, 94.6mm, 149.8mm) (InComponentClass('7SA'))
+Processing Rule : Board Clearance Constraint (Gap=0mm) (OnLayer('Top Overlay'))
 Rule Violations :0
 
 Processing Rule : Room 7SB (Bounding Region = (79.6mm, 96.5mm, 94.6mm, 123.4mm) (InComponentClass('7SB'))
 Rule Violations :0
 
+Processing Rule : Room 7SA (Bounding Region = (79.65mm, 123.1mm, 94.6mm, 149.8mm) (InComponentClass('7SA'))
+Rule Violations :0
+
 Processing Rule : Room 7SC (Bounding Region = (79.65mm, 70.15mm, 94.6mm, 96.85mm) (InComponentClass('7SC'))
 Rule Violations :0
 
@@ -73,12 +73,12 @@ Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (Al
 Rule Violations :0
 
 Waived Violations Of Rule : Minimum Solder Mask Sliver (Gap=0.152mm) (All),(All)
-   Waived Violation between Minimum Solder Mask Sliver Constraint: (0.047mm < 0.152mm) Between Track (5.717mm,13.609mm)(10.738mm,13.609mm) on Top Solder And Track (3.122mm,13.162mm)(5.717mm,13.162mm) on Top Solder [Top Solder] Mask Sliver [0.047mm]Waived by  at 31/12/2019 17:22:31Logo exclu des vérifications
-   Waived Violation between Minimum Solder Mask Sliver Constraint: (0.088mm < 0.152mm) Between Track (5.18mm,10.268mm)(9.058mm,10.278mm) on Top Solder And Track (8.581mm,10.765mm)(8.581mm,11.591mm) on Top Solder [Top Solder] Mask Sliver [0.088mm]Waived by  at 31/12/2019 17:22:26Logo exclu des vérifications
-   Waived Violation between Minimum Solder Mask Sliver Constraint: (0.046mm < 0.152mm) Between Track (5.637mm,10.716mm)(5.637mm,11.64mm) on Top Solder And Track (5.18mm,10.268mm)(9.058mm,10.278mm) on Top Solder [Top Solder] Mask Sliver [0.046mm]Waived by  at 31/12/2019 17:22:05Logo exclu des vérifications
+   Waived Violation between Minimum Solder Mask Sliver Constraint: (0.046mm < 0.152mm) Between Track (5.18mm,10.268mm)(9.058mm,10.278mm) on Top Solder And Track (5.637mm,10.716mm)(5.637mm,11.64mm) on Top Solder [Top Solder] Mask Sliver [0.046mm]Waived by  at 31/12/2019 17:22:05Logo exclu des vérifications
+   Waived Violation between Minimum Solder Mask Sliver Constraint: (0.088mm < 0.152mm) Between Track (8.581mm,10.765mm)(8.581mm,11.591mm) on Top Solder And Track (5.18mm,10.268mm)(9.058mm,10.278mm) on Top Solder [Top Solder] Mask Sliver [0.088mm]Waived by  at 31/12/2019 17:22:26Logo exclu des vérifications
+   Waived Violation between Minimum Solder Mask Sliver Constraint: (0.047mm < 0.152mm) Between Track (3.122mm,13.162mm)(5.717mm,13.162mm) on Top Solder And Track (5.717mm,13.609mm)(10.738mm,13.609mm) on Top Solder [Top Solder] Mask Sliver [0.047mm]Waived by  at 31/12/2019 17:22:31Logo exclu des vérifications
 Waived Violations :3
 
 
 Violations Detected : 0
 Waived Violations : 3
-Time Elapsed        : 00:00:04
\ No newline at end of file
+Time Elapsed        : 00:00:03
\ No newline at end of file
diff --git a/Project Outputs for Testeur_de_cable/Design Rule Check - Carte.html b/Project Outputs for Testeur_de_cable/Design Rule Check - Carte.html
index a83c5023db11b045d1b4a7edc8cacd8dd007b6ea..560fc5bd300cddbdf83ea60432274689ab3c0bd2 100644
--- a/Project Outputs for Testeur_de_cable/Design Rule Check - Carte.html	
+++ b/Project Outputs for Testeur_de_cable/Design Rule Check - Carte.html	
@@ -219,17 +219,17 @@
 <tr class="front_matter">
 <td class="front_matter_column1">Date:</td>
 <td class="front_matter_column2"></td>
-<td class="front_matter_column3">31/12/2019</td>
+<td class="front_matter_column3">01/01/2020</td>
 </tr>
 <tr class="front_matter">
 <td class="front_matter_column1">Time:</td>
 <td class="front_matter_column2"></td>
-<td class="front_matter_column3">19:50:44</td>
+<td class="front_matter_column3">01:15:59</td>
 </tr>
 <tr class="front_matter">
 <td class="front_matter_column1">Elapsed Time:</td>
 <td class="front_matter_column2"></td>
-<td class="front_matter_column3">00:00:04</td>
+<td class="front_matter_column3">00:00:03</td>
 </tr>
 <tr class="front_matter">
 <td class="front_matter_column1">Filename:</td>
@@ -254,7 +254,7 @@
 <td class="DRC_summary_header_col3" style="color : red">3</td></tr>
 </table>
 </td>
-</table><a name="IDOQYQFZVRBCCVHTITMCXQ3OWN2D5NZNGATBBHBOMLCZVAGDSTCOXF"><h2>Summary</h2></a><table>
+</table><a name="IDLNZYWUHAIOJSKACEC1DAE24LEOWQGC53WUSIFXK2GVTPWFUSPIWL"><h2>Summary</h2></a><table>
 <tr>
 <th class="column1">Warnings</th>
 <th class="column2">Count</th>
@@ -269,95 +269,95 @@
 <th class="column2">Count</th>
 </tr>
 <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
-<td class="column1"><a href="#IDTL3JFZVK2ONVEJYQDDVFT0AMQKLJG3LBHXAL2QEEWNLZIPLTHZAC">Clearance Constraint (Gap=0.152mm) (All),(All)</a></td>
+<td class="column1"><a href="#ID01GBJH2WHFBKICMV3Y3MBO330NGV5LZ1DEPLOFOCIZA03DHP1RRP">Clearance Constraint (Gap=0.152mm) (All),(All)</a></td>
 <td class="column2">0</td>
 </tr>
 <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
-<td class="column1"><a href="#ID3BAL31RDMDKDGVB2K1PEUPG4REQGXD3ICXZVMWESTCVITOK5XS0C">Short-Circuit Constraint (Allowed=No) (All),(All)</a></td>
+<td class="column1"><a href="#IDHAYUVICA0BERC0YBINDLOXADCNXFUGU0IEO20CF34BNJFTVWLRRI">Short-Circuit Constraint (Allowed=No) (All),(All)</a></td>
 <td class="column2">0</td>
 </tr>
 <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
-<td class="column1"><a href="#ID1DNDF1NJBTFIOL10XLDJST1ZXNDUVPX0XNXOINBZMSP020YCJ10C">Un-Routed Net Constraint ( (All) )</a></td>
+<td class="column1"><a href="#IDPHPSNEEB1SVKEDPCD3T1DSHWIG35NOMTIBTKGYJLMWHHQG0AVQ0N">Un-Routed Net Constraint ( (All) )</a></td>
 <td class="column2">0</td>
 </tr>
 <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
-<td class="column1"><a href="#IDWHCQQVRSMBMOLXKGKZZGJMLNBKCNQZJ0CYBRYFKS5PSUBYJYCRTJ">Modified Polygon (Allow modified: No), (Allow shelved: No)</a></td>
+<td class="column1"><a href="#IDUHXL5KNJJTJQLQLA4RHTLZD3QBYKKXZ55WIMWNB3XP14LU1ZDX3C">Modified Polygon (Allow modified: No), (Allow shelved: No)</a></td>
 <td class="column2">0</td>
 </tr>
 <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
-<td class="column1"><a href="#IDRGZXDFVAISCIP0NS2X2UBCXLBIKCDK2WBPELRNKMVQUYD1SKS1BG">Width Constraint (Min=0.2mm) (Max=0.5mm) (Preferred=0.254mm) (OnLayer('Top Layer'))</a></td>
+<td class="column1"><a href="#IDJ5C4QCPMVQOGMV4IX3RP4TIIGJ2TTSSFMJ1JACPFWCJWR2JTV0O">Width Constraint (Min=0.2mm) (Max=0.5mm) (Preferred=0.254mm) (OnLayer('Top Layer'))</a></td>
 <td class="column2">0</td>
 </tr>
 <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
-<td class="column1"><a href="#ID0XJSF0I4XARVEVLWTYGCIJVIFH3NX4UBLQ2SFXFC5IACJ54TLAHJ">Width Constraint (Min=0.1mm) (Max=0.4mm) (Preferred=0.254mm) (OnLayer('Top Overlay'))</a></td>
+<td class="column1"><a href="#IDQ33T0GGCLU1AHVR1CFDVJCJ2UDSXIMA2IATRDDLAB5A3ODJZUEOM">Width Constraint (Min=0.2mm) (Max=0.5mm) (Preferred=0.254mm) (OnLayer('Bottom Layer'))</a></td>
 <td class="column2">0</td>
 </tr>
 <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
-<td class="column1"><a href="#IDNFWUJJV4ZCBBHQSTNXCJAMM2SHP1QRY3HVC0OFKX15MXBUV451II">Width Constraint (Min=0.2mm) (Max=0.5mm) (Preferred=0.254mm) (OnLayer('Bottom Layer'))</a></td>
+<td class="column1"><a href="#IDD35TZTZD5MKKDTEAIJIIBVWZABNZJCKC3BTDIJEIRI4JH0QAUCFB">Width Constraint (Min=0.1mm) (Max=0.4mm) (Preferred=0.254mm) (OnLayer('Top Overlay'))</a></td>
 <td class="column2">0</td>
 </tr>
 <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
-<td class="column1"><a href="#IDDJHXH1RLUUBWJI5AZWQLJOGPOFH2Z3GEYGF1HSC2AC4MRSDKD5EF">Width Constraint (Min=0.1mm) (Max=0.4mm) (Preferred=0.254mm) (OnLayer('Bottom Overlay'))</a></td>
+<td class="column1"><a href="#IDFE5TFYD1NGANER3SX55L1MI0YNFTJN4LXSSKYAKAANDQXKSOMGKP">Width Constraint (Min=0.1mm) (Max=0.4mm) (Preferred=0.254mm) (OnLayer('Bottom Overlay'))</a></td>
 <td class="column2">0</td>
 </tr>
 <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
-<td class="column1"><a href="#IDMXBUZH5O0CWZDBVGUYAXIYHQGCPRP5GU4E0QDLD5YJIVUTF111XL">Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)</a></td>
+<td class="column1"><a href="#IDJWUHPA4B0JWXDVU1QCTC213T3GVW0WURF2B2RBB1PNI0YYDQQXEP">Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)</a></td>
 <td class="column2">0</td>
 </tr>
 <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
-<td class="column1"><a href="#IDLGP31PQWDCEHOB30B51NM2E4GGYWIJLN2LO3NJKFFW3EMELFKVQI">Minimum Annular Ring (Minimum=0.128mm) (All)</a></td>
+<td class="column1"><a href="#IDTYDHHHUX3AVGDJBTCQ4LR5Y3HFAGTZPSIQVHFADITUIRFDC5Y02O">Minimum Annular Ring (Minimum=0.128mm) (All)</a></td>
 <td class="column2">0</td>
 </tr>
 <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
-<td class="column1"><a href="#IDGA3QT0XPM4O4EDTFMHHGY420TCXRTSUC5ZJ5X4NMOOBITATLYCI">Hole Size Constraint (Min=0.254mm) (Max=25.4mm) (All)</a></td>
+<td class="column1"><a href="#IDKHHSTFJQRUPZKPXHGQLGFT4DCEI4H1KHEHN2J4CEYOHNRPFCRO">Hole Size Constraint (Min=0.254mm) (Max=25.4mm) (All)</a></td>
 <td class="column2">0</td>
 </tr>
 <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
-<td class="column1"><a href="#IDYW3INRFJQMAYLCQUXEWAH5BBGEV03SMAFRNP1IGE5FCPMZS4I5QI">Hole To Hole Clearance (Gap=0.254mm) (All),(All)</a></td>
+<td class="column1"><a href="#IDMFVCZ0YPEPJ3KPINXC0CQTBYEN20JWUVN5VTSSBZXJGMSXUV1RPB">Hole To Hole Clearance (Gap=0.254mm) (All),(All)</a></td>
 <td class="column2">0</td>
 </tr>
 <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
-<td class="column1"><a href="#IDYIQ2FABXQ1XXOGFTT5O5LMFJHLQLAKL2LNGHKCHNMYSNM30DFP4O">Minimum Solder Mask Sliver (Gap=0.152mm) (All),(All)</a></td>
+<td class="column1"><a href="#ID4411X1CTLJWTDUROBQQRYGDFYCG1KLA3CINRLQBDWXTOH55ZESXJ">Minimum Solder Mask Sliver (Gap=0.152mm) (All),(All)</a></td>
 <td class="column2">0</td>
 </tr>
 <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
-<td class="column1"><a href="#ID3WBCL4QTKL1SDSPM3FTPBREJXDBXFWFPJIS42XNLKHTIKMREPLED">Silk To Solder Mask (Clearance=0.102mm) (Disabled)(IsPad),(All)</a></td>
+<td class="column1"><a href="#IDVZYLN2IU3QOTM1MXDT2ANSQBVEQHNZF3QWKJGGJ23EF4E2WV2JPL">Silk To Solder Mask (Clearance=0.102mm) (Disabled)(IsPad),(All)</a></td>
 <td class="column2">0</td>
 </tr>
 <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
-<td class="column1"><a href="#IDIRCENCQ2QYA1GOC2KYXROG4LMEUCK2LGNFALVMWKAHVN4S2Z5ZF">Silk to Silk (Clearance=0.254mm) (Disabled)(All),(All)</a></td>
+<td class="column1"><a href="#IDB1CDZUL21GF2P12AVI02QW2BEOCSSXJ11KNY2ZDAXPDFO0MY4FCK">Silk to Silk (Clearance=0.254mm) (Disabled)(All),(All)</a></td>
 <td class="column2">0</td>
 </tr>
 <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
-<td class="column1"><a href="#IDHASRIN3RLBOGOKZ4SZ50T4B1LCN0U2HS3F11M1OTA4GVB5V05SHD">Net Antennae (Tolerance=0mm) (All)</a></td>
+<td class="column1"><a href="#IDT1FMKICV01PRBDJJ3NURHEMOGBUBVE2QFQODSTIJTZADDANBVDCF">Net Antennae (Tolerance=0mm) (All)</a></td>
 <td class="column2">0</td>
 </tr>
 <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
-<td class="column1"><a href="#ID1ZGMOIPWHU15I01VMNN5FLJT5HUQUNVRQ2OZXKIOL2VWUQOAWVLD">Board Clearance Constraint (Gap=0mm) (OnLayer('Top Overlay'))</a></td>
+<td class="column1"><a href="#IDWR2RVSFD31D3MJ2ZEB2OM4ZYEM1U45JV51BRGNDVE0LU5TJBBXUJ">Board Clearance Constraint (Gap=0mm) (All)</a></td>
 <td class="column2">0</td>
 </tr>
 <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
-<td class="column1"><a href="#IDMRLAJH1BWQPDEJ1DHI2VOT2ZAI55AWPZXL2ICNHVYJ0E5X4GA4BF">Board Clearance Constraint (Gap=0mm) (All)</a></td>
+<td class="column1"><a href="#IDLZQYOWS1DJYXOZVX14YKF2REEG3KWB4POSYDR3CIBN3L0LHGTD4C">Board Clearance Constraint (Gap=0mm) (OnLayer('Top Overlay'))</a></td>
 <td class="column2">0</td>
 </tr>
 <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
-<td class="column1"><a href="#IDFKVXSVOH3C4DBBQ1ZOV05UR5QHQN5E3QF0O2TWPTHEEVR3MI5JVG">Room 7SA (Bounding Region = (79.65mm, 123.1mm, 94.6mm, 149.8mm) (InComponentClass('7SA'))</a></td>
+<td class="column1"><a href="#IDJRPCBCTFJFAZDMFRRJJ3NSKB0BYWXSGQPELNWVFMXNT0FHLB3S">Room 7SB (Bounding Region = (79.6mm, 96.5mm, 94.6mm, 123.4mm) (InComponentClass('7SB'))</a></td>
 <td class="column2">0</td>
 </tr>
 <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
-<td class="column1"><a href="#IDUUBEND5YOJLCCOTP2UAHEAQMKLJBZ2GTKCUX23LGM1FBG1XEVBYK">Room 7SB (Bounding Region = (79.6mm, 96.5mm, 94.6mm, 123.4mm) (InComponentClass('7SB'))</a></td>
+<td class="column1"><a href="#ID4424PSU03T0CCV1Y4GKZXHD44F43ND0O4DB0K3BFKHEDNO3N4APO">Room 7SA (Bounding Region = (79.65mm, 123.1mm, 94.6mm, 149.8mm) (InComponentClass('7SA'))</a></td>
 <td class="column2">0</td>
 </tr>
 <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
-<td class="column1"><a href="#IDVPZA5D2J1LRVEOO4ZYDB2N0PZRUB0RH25O0AEJ4LJI0RC2SX4LM">Room 7SC (Bounding Region = (79.65mm, 70.15mm, 94.6mm, 96.85mm) (InComponentClass('7SC'))</a></td>
+<td class="column1"><a href="#IDBFMCKNJTEC5LCXPBTNC0KL0APNFCSGW4DHUY3FMM3P5020SYRZR">Room 7SC (Bounding Region = (79.65mm, 70.15mm, 94.6mm, 96.85mm) (InComponentClass('7SC'))</a></td>
 <td class="column2">0</td>
 </tr>
 <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
-<td class="column1"><a href="#IDM0AAZBQCJ4ZSP4GS3TQVCITGFKQVJ3443TFDG2OLTA4G3OXQNEPN">Room 7SD (Bounding Region = (79.6mm, 43.55mm, 94.6mm, 70.3mm) (InComponentClass('7SD'))</a></td>
+<td class="column1"><a href="#IDSC1B5H0DOOHGIKZAWKQR4QPAFKOAM54MVNZO4OL3NJM1CJMXDTLL">Room 7SD (Bounding Region = (79.6mm, 43.55mm, 94.6mm, 70.3mm) (InComponentClass('7SD'))</a></td>
 <td class="column2">0</td>
 </tr>
 <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
-<td class="column1"><a href="#ID0SUJOI4M4ABFKYV004W3F43UWFOEYGXR3TJXJSDTCSEIKWKQQRSL">Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)</a></td>
+<td class="column1"><a href="#ID22JWITC2RESEDM2LVWCNMUQD4BY0XG0SDB3V3MK0T0X5HOBPOM2D">Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)</a></td>
 <td class="column2">0</td>
 </tr>
 <tr>
@@ -370,25 +370,25 @@
 <th class="column2">Count</th>
 </tr>
 <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
-<td class="column1"><a href="#IDL4AWKPPEMA11K3BAAGR5HELXLK1O3HQWNTWR4NLJO14AWEBK5CXD">Minimum Solder Mask Sliver (Gap=0.152mm) (All),(All)</a></td>
+<td class="column1"><a href="#ID5AFZZ51CQRCJKDOKEA2XAS10YM01LE1IYPPNJLF1S2Q0KFVXFZMF">Minimum Solder Mask Sliver (Gap=0.152mm) (All),(All)</a></td>
 <td class="column2">3</td>
 </tr>
 <tr>
 <td style="font-weight : bold; text-align : right" class="column1">Total</td>
 <td style="font-weight : bold" class="column2">3</td>
 </tr>
-</table><br><a name="ID3CGKZM5AUGHFHBKC5O4BT4RIAOWUFCAL55S05CKTNCIQTY2FMGKK"><h2>Rule Violations</h2></a><a name="IDRU0JR4XTOHYQOETCE24IIZBDVN4WEAHIHJZKITPK3S3SCJUJPD5P"><h2>Waived Violations</h2></a><a name="IDL4AWKPPEMA11K3BAAGR5HELXLK1O3HQWNTWR4NLJO14AWEBK5CXD"><table>
+</table><br><a name="IDFU1JKD23C51UGW1YJUBM12RSVL3S0DB32YBJ1FCBL2O5SXAW5AM"><h2>Rule Violations</h2></a><a name="ID4DVZFEQC4PVWBAC1E5INXSTXUKQIGXIB0CBSS1IP2LZLHCSVBDOJ"><h2>Waived Violations</h2></a><a name="ID5AFZZ51CQRCJKDOKEA2XAS10YM01LE1IYPPNJLF1S2Q0KFVXFZMF"><table>
 <tr>
 <th style="text-align : left" colspan="1" class="waived">Minimum Solder Mask Sliver (Gap=0.152mm) (All),(All)</th>
 </tr>
 <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
-<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\Yann Roberge\Documents\Ing%C3%A9\A2019\Testeur de c%C3%A2ble\PCB_Project\Carte.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1205.705mil|Location2.X=1212.955mil|Location1.Y=1507.616mil|Location2.Y=1514.866mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\Yann Roberge\Documents\Ingé\A2019\Testeur de câble\PCB_Project\Carte.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1205.705mil|Location2.X=1212.955mil|Location1.Y=1507.616mil|Location2.Y=1514.866mil|Absolute=True">Minimum Solder Mask Sliver Constraint: (0.047mm &lt; 0.152mm) Between Track (5.717mm,13.609mm)(10.738mm,13.609mm) on Top Solder And Track (3.122mm,13.162mm)(5.717mm,13.162mm) on Top Solder [Top Solder] Mask Sliver [0.047mm]</acronym></a><br>Waived by  at 31/12/2019 17:22:31<br>Logo exclu des vérifications</td>
+<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\Yann Roberge\Documents\Ing%C3%A9\A2019\Testeur de c%C3%A2ble\PCB_Project\Carte.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1202.595mil|Location2.X=1209.845mil|Location1.Y=1393.719mil|Location2.Y=1400.969mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\Yann Roberge\Documents\Ingé\A2019\Testeur de câble\PCB_Project\Carte.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1202.595mil|Location2.X=1209.845mil|Location1.Y=1393.719mil|Location2.Y=1400.969mil|Absolute=True">Minimum Solder Mask Sliver Constraint: (0.046mm &lt; 0.152mm) Between Track (5.18mm,10.268mm)(9.058mm,10.278mm) on Top Solder And Track (5.637mm,10.716mm)(5.637mm,11.64mm) on Top Solder [Top Solder] Mask Sliver [0.046mm]</acronym></a><br>Waived by  at 31/12/2019 17:22:05<br>Logo exclu des vérifications</td>
 </tr>
 <tr class="onmouseout_even" onmouseover="className = 'onmouseover_even'" onmouseout="className = 'onmouseout_even'">
-<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\Yann Roberge\Documents\Ing%C3%A9\A2019\Testeur de c%C3%A2ble\PCB_Project\Carte.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1318.475mil|Location2.X=1325.725mil|Location1.Y=1394.847mil|Location2.Y=1402.097mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\Yann Roberge\Documents\Ingé\A2019\Testeur de câble\PCB_Project\Carte.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1318.475mil|Location2.X=1325.725mil|Location1.Y=1394.847mil|Location2.Y=1402.097mil|Absolute=True">Minimum Solder Mask Sliver Constraint: (0.088mm &lt; 0.152mm) Between Track (5.18mm,10.268mm)(9.058mm,10.278mm) on Top Solder And Track (8.581mm,10.765mm)(8.581mm,11.591mm) on Top Solder [Top Solder] Mask Sliver [0.088mm]</acronym></a><br>Waived by  at 31/12/2019 17:22:26<br>Logo exclu des vérifications</td>
+<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\Yann Roberge\Documents\Ing%C3%A9\A2019\Testeur de c%C3%A2ble\PCB_Project\Carte.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1318.475mil|Location2.X=1325.725mil|Location1.Y=1394.847mil|Location2.Y=1402.097mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\Yann Roberge\Documents\Ingé\A2019\Testeur de câble\PCB_Project\Carte.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1318.475mil|Location2.X=1325.725mil|Location1.Y=1394.847mil|Location2.Y=1402.097mil|Absolute=True">Minimum Solder Mask Sliver Constraint: (0.088mm &lt; 0.152mm) Between Track (8.581mm,10.765mm)(8.581mm,11.591mm) on Top Solder And Track (5.18mm,10.268mm)(9.058mm,10.278mm) on Top Solder [Top Solder] Mask Sliver [0.088mm]</acronym></a><br>Waived by  at 31/12/2019 17:22:26<br>Logo exclu des vérifications</td>
 </tr>
 <tr class="onmouseout_odd" onmouseover="className = 'onmouseover_odd'" onmouseout="className = 'onmouseout_odd'">
-<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\Yann Roberge\Documents\Ing%C3%A9\A2019\Testeur de c%C3%A2ble\PCB_Project\Carte.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1202.595mil|Location2.X=1209.845mil|Location1.Y=1393.719mil|Location2.Y=1400.969mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\Yann Roberge\Documents\Ingé\A2019\Testeur de câble\PCB_Project\Carte.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1202.595mil|Location2.X=1209.845mil|Location1.Y=1393.719mil|Location2.Y=1400.969mil|Absolute=True">Minimum Solder Mask Sliver Constraint: (0.046mm &lt; 0.152mm) Between Track (5.637mm,10.716mm)(5.637mm,11.64mm) on Top Solder And Track (5.18mm,10.268mm)(9.058mm,10.278mm) on Top Solder [Top Solder] Mask Sliver [0.046mm]</acronym></a><br>Waived by  at 31/12/2019 17:22:05<br>Logo exclu des vérifications</td>
+<td class="column1"><a href="dxpprocess://PCB:Zoom?document=C:\Users\Yann Roberge\Documents\Ing%C3%A9\A2019\Testeur de c%C3%A2ble\PCB_Project\Carte.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1205.705mil|Location2.X=1212.955mil|Location1.Y=1507.616mil|Location2.Y=1514.866mil|Absolute=True" class="callback"><acronym title="dxpprocess://PCB:Zoom?document=C:\Users\Yann Roberge\Documents\Ingé\A2019\Testeur de câble\PCB_Project\Carte.PcbDoc;viewname=PCBEditor;Action=AREA_DYNAMICZOOM|Location1.X=1205.705mil|Location2.X=1212.955mil|Location1.Y=1507.616mil|Location2.Y=1514.866mil|Absolute=True">Minimum Solder Mask Sliver Constraint: (0.047mm &lt; 0.152mm) Between Track (3.122mm,13.162mm)(5.717mm,13.162mm) on Top Solder And Track (5.717mm,13.609mm)(10.738mm,13.609mm) on Top Solder [Top Solder] Mask Sliver [0.047mm]</acronym></a><br>Waived by  at 31/12/2019 17:22:31<br>Logo exclu des vérifications</td>
 </tr>
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