-------------------------------------------------------------------------------
-- Project  ELE8304 : Circuits intégrés à très grande échelle
-------------------------------------------------------------------------------
-- File     wb.vhd
-- Authors  Titouan Luard <luardtitouan@gmail.com> 
--          Yann Roberge <yann.roberge@polymtl.ca> 
-- Lab      GRM - Polytechnique Montreal
-- Date     2021-10-29
-------------------------------------------------------------------------------
-- Brief   
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;


library work;
use work.riscv_pkg.all;

entity wb is
  
  port (
    i_dmem_read   : in std_logic_vector(XLEN-1 downto 0);

    --i_memory_reg : in memory_reg;
    i_opcode      : in  std_logic_vector(OPCODE_WIDTH-1 downto 0);
    i_alu_result  : in  std_logic_vector(XLEN-1 downto 0);
    i_rd_addr     : in  std_logic_vector(REG_WIDTH-1 downto 0);   

    o_write_back: out write_back_reg
    --o_rd_data     : out std_logic_vector(XLEN-1 downto 0);
    --o_rd_addr :   out std_logic_vector(9 downto 0));

    --o_we : out std_logic
  );

end entity wb;

architecture beh of wb is
begin

  o_write_back.opcode <= i_opcode;
  
  o_write_back.wr_addr <= i_rd_addr;
  with i_opcode select o_write_back.wr_data <=
    i_dmem_read when OPCODE_LW,
    i_alu_result when others;
  
  with i_opcode select o_write_back.we <=
    '0' when OPCODE_SW | OPCODE_BEQ,
    '1' when others;
  
end architecture beh;