-------------------------------------------------------------------------------
-- Project  ELE8304 : Circuits intégrés à très grande échelle
-------------------------------------------------------------------------------
-- File     memory_access.vhd
-- Authors  Titouan Luard <luardtitouan@gmail.com> 
--          Yann Roberge <yann.roberge@polymtl.ca> 
-- Lab      GRM - Polytechnique Montreal
-- Date     2021-10-29
-------------------------------------------------------------------------------
-- Brief   
------------------------------------------------------------------------
-------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;


library work;
use work.riscv_pkg.all;

entity memory_access is
  generic (RESET_VECTOR : std_logic_vector(XLEN-1 downto 0) := (others => '0'));
  port (
  
    i_clk :       in std_logic;
    i_store_data : in std_logic;
    i_alu_result : in std_logic_vector(XLEN-1 downto 0);
    i_rd_addr :   in std_logic_vector(9 downto 0);
    i_rstn: in std_logic;
        
    o_alu_result: out std_logic_vector(XLEN-1 downto 0);
    o_dmem_read:  out std_logic_vector(XLEN-1 downto 0);
    o_rd_addr :   out std_logic_vector(9 downto 0);
    --communication avec la DPM
    i_dmem_read:  in std_logic_vector(XLEN-1 downto 0 );
    
    o_dmem_addr:  out std_logic_vector(9 downto 0);
    o_dmem_en:    out std_logic);

end entity memory_access;

architecture beh of memory_access is

signal temp_alu_result : std_logic_vector(XLEN-1 downto 0);
signal temp_rd_addr :std_logic_vector(9 downto 0);
signal dmem_addr :std_logic_vector(9 downto 0);
begin

dmem_addr <= i_alu_result(9 downto 0);
o_dmem_addr <= dmem_addr;
o_dmem_en <= i_store_data;
o_dmem_read<=i_dmem_read;

process (i_clk, i_rstn) is
  begin
    if i_rstn = '0' then
      o_alu_result <= (others => '0') ;
      o_rd_addr <= (others => '0')  ;    
    else
      if rising_edge(i_clk) then
        o_alu_result <= i_alu_result; 

        o_rd_addr <= i_rd_addr;

      end if;
    end if;
         
end process ;


end architecture beh;