-------------------------------------------------------------------------------
-- Project  ELE8304 : Circuits intégrés à très grande échelle
-------------------------------------------------------------------------------
-- File     memory_access.vhd
-- Authors  Titouan Luard <luardtitouan@gmail.com> 
--          Yann Roberge <yann.roberge@polymtl.ca> 
-- Lab      GRM - Polytechnique Montreal
-- Date     2021-12-04
-------------------------------------------------------------------------------
-- Brief   
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;


library work;
use work.riscv_pkg.all;

entity memory_access is
  port (
    -- Entrées provenant de l'extérieur du pipeline
    i_clk        : in std_logic;
    i_rstn       : in std_logic;

    -- Entrées provenant de l'étage Execute
    i_execute_reg : in execute_reg;
    --i_store_data : in std_logic_vector(XLEN-1 downto 0);
    --i_alu_result : in std_logic_vector(XLEN-1 downto 0);
    --i_rd_addr    : in std_logic_vector(DMEM_ADDR_WIDTH-1 downto 0);

    -- Sorties
    o_memory_reg : out memory_reg;
    o_dmem_read  : out std_logic_vector(XLEN-1 downto 0);
    --o_alu_result : out std_logic_vector(XLEN-1 downto 0);
    --o_rd_addr    : out std_logic_vector(DMEM_ADDR_WIDTH-1 downto 0);

    -- Communication avec la DPM
    i_dmem_read  : in std_logic_vector(XLEN-1 downto 0 );
    -- le +1 laisse 2 bits en plus pour qu'on puisse diviser par 4 ensuite
    o_dmem_addr  : out std_logic_vector(DMEM_ADDR_WIDTH+1 downto 0);
    o_dmem_write : out std_logic_vector(XLEN-1 downto 0);
    o_dmem_we    : out std_logic;
    o_dmem_en    : out std_logic);

end entity memory_access;

architecture beh of memory_access is

  -- Signaux internes
  --signal temp_alu_result : std_logic_vector(XLEN-1 downto 0);
  --signal temp_rd_addr    : std_logic_vector(DMEM_ADDR_WIDTH-1 downto 0);

  alias opcode is i_execute_reg.opcode;
begin

-- Contrôle d'interface mémoire
with i_rstn select o_dmem_en <=
  '1' when '1',
  '0' when others;
o_dmem_addr <= i_execute_reg.alu_result(DMEM_ADDR_WIDTH+1 downto 0);
o_dmem_read <= i_dmem_read;

-- Écriture en mémoire
o_dmem_we <= '1' when opcode = OPCODE_SW else '0';
o_dmem_write <= i_execute_reg.store_data;

-- Recopiage des signaux tirés de Execute dans le registre ME/WB
process (i_clk) is
begin
  if rising_edge(i_clk) then
    if i_rstn = '1' then
      o_memory_reg.opcode     <= opcode;
      o_memory_reg.alu_result <= i_execute_reg.alu_result;
      o_memory_reg.rd_addr    <= i_execute_reg.rd_addr;
    else
      o_memory_reg.opcode     <= (others => '0');
      o_memory_reg.alu_result <= (others => '0');
      o_memory_reg.rd_addr    <= (others => '0');
    end if;
  end if;

--  if i_rstn = '0' then
--    --o_alu_result <= (others => '0');
--    --o_rd_addr <= (others => '0');    
--  else
--    if rising_edge(i_clk) then
--      --o_alu_result <= i_alu_result; 
--      --o_rd_addr <= i_rd_addr;
--    end if;
--  end if;
         
end process;


end architecture beh;