-------------------------------------------------------------------------------
-- Project  ELE8304 : Circuits intégrés à très grande échelle
-------------------------------------------------------------------------------
-- File     fetch_tb.vhd
-- Authors  Titouan Luard <luardtitouan@gmail.com> 
--          Yann Roberge <yann.roberge@polymtl.ca> 
-- Lab      GRM - Polytechnique Montreal
-- Date     2021-11-19
-------------------------------------------------------------------------------
-- Brief    test bench of the fetche
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;

library work;
use work.riscv_pkg.all;

entity fetch_tb is
end fetch_tb;

architecture tb of fetch_tb is

    constant XLEN   : positive := 32;

    signal target    : std_logic_vector(XLEN-1 downto 0);
    signal clk       : std_logic;
    signal stall     : std_logic;
    signal transfert : std_logic;
    signal rstn      : std_logic;
    signal flush     : std_logic;
    signal mem_read  : std_logic_vector(XLEN-1 downto 0);
    signal mem_addr  : std_logic_vector(IMEM_ADDR_WIDTH-1 downto 0);
    
    signal fetch_reg : fetch_reg;
    alias pc    is fetch_reg.pc;
    alias fetch is fetch_reg.instruction;
    --signal pc        : std_logic_vector(XLEN-1 downto 0);
    --signal fetch     : std_logic_vector(XLEN-1 downto 0);    

    --signal expected_result_pc : std_logic_vector(IMEM_ADDR_WIDTH-1 downto 0);
    signal expected_result_pc : std_logic_vector(XLEN-1 downto 0);
    signal expected_result_fetch : std_logic_vector(XLEN-1 downto 0);
    signal expected_result_mem_addr : std_logic_vector(IMEM_ADDR_WIDTH-1 downto 0);
    constant PERIOD   : time := 10 ns;

begin

  -- DUT
  dut: entity work.fetch
    generic map (
      RESET_VECTOR => (others => '0')
    )
    port map (
      i_target => target,
      i_clk   => clk,
      i_stall => stall,
      i_transfert => transfert,
      i_mem_read => mem_read,
      i_rstn  => rstn,
      i_flush => flush,
      o_fetch_reg => fetch_reg,
      o_mem_addr => mem_addr
    );

  drive_clk : process
  begin
    clk <= '0';
    wait for PERIOD/2;
    clk <= '1';
    wait for PERIOD/2;
  end process drive_clk;

  -- Main TB process
  --TODO: ADAPTER LE TB
  p_main : process
  begin
    -- Vecteurs de tests

    report "BEGIN SIMULATION";
    --t=0 ns

    report "initialisation";
    
    rstn      <= '0' ;
    target    <= (1 downto 0 => '1', others => '0');
    stall     <= '0';
    transfert <= '0';
    flush     <= '0';
    
    expected_result_pc <= (others => '0');
    expected_result_fetch <= (others => '0');
    expected_result_mem_addr <= (others => '0'); 


    wait for PERIOD; --10 ns
    
    assert fetch = expected_result_fetch 
      report "fetch error" severity error;
    assert mem_addr = expected_result_mem_addr
      report "mem addr" severity error; 
  
    rstn  <= '1';
    mem_read <= (others => '1'); 
     
    expected_result_mem_addr    <= (2 downto 0 => "100", others => '0');
    expected_result_fetch <= (others => '1');   
    wait for PERIOD; --20 ns
    

    assert fetch = expected_result_fetch 
      report "fetch error" severity error;
    assert mem_addr = expected_result_mem_addr
      report "mem addr" severity error;   
    expected_result_mem_addr    <= (3 downto 0 => "1000", others => '0');
    expected_result_fetch <= (1 downto 0 => "10", others => '0');  
    
    mem_read <= (1 downto 0 => "10", others => '0');      
            
    
    wait for PERIOD; --30ns
    
    assert fetch = expected_result_fetch 
      report "fetch error" severity error;
    assert mem_addr = expected_result_mem_addr 
      report "mem addr" severity error;
    expected_result_mem_addr    <= (1 downto 0 => '1', others => '0');
    expected_result_fetch <= (4 downto 0 => "11111", others => '0'); 
      
    transfert <= '1';
    target    <= (1 downto 0 => '1', others => '0');  
    mem_read  <= (4 downto 0 => "11111", others => '0'); 
    
           
    
    wait for PERIOD; --40 ns

    assert fetch = expected_result_fetch 
      report "fetch error" severity error;
    assert mem_addr = expected_result_mem_addr
      report "mem addr" severity error;
      
      
    stall <= '1';
    transfert <= '0';    
      

    wait for PERIOD; --50 ns
    assert fetch = expected_result_fetch 
      report "fetch error" severity error;
    assert mem_addr = expected_result_mem_addr
      report "mem addr" severity error;     
      
    stall <= '0';
    flush <= '1';    
       
    expected_result_mem_addr    <= (2 downto 0 => "111", others => '0');
    expected_result_fetch <= (others => '0');           

    wait for PERIOD; --60 ns
    
    assert fetch = expected_result_fetch 
      report "fetch error" severity error;
    assert mem_addr = expected_result_mem_addr
      report "mem addr" severity error;
    rstn <= '0';
    
    expected_result_pc    <= (others => '0');
    expected_result_fetch <= (others => '0'); 
    
    wait for PERIOD; --70 ns    

    assert fetch = expected_result_fetch 
      report "fetch error" severity error;
    assert mem_addr = expected_result_mem_addr
      report "mem addr" severity error;
      

    report "SIMULATION DONE";
    wait;
  end process p_main;

end architecture tb;