-------------------------------------------------------------------------------
-- Project  ELE8304 : Circuits intégrés à très grande échelle
-------------------------------------------------------------------------------
-- File     riscv_decode.vhd
-- Authors  Titouan Luard <luardtitouan@gmail.com> 
--          Yann Roberge <yann.roberge@polymtl.ca> 
-- Lab      ELE8304-9
-- Date     2021-11-28
-------------------------------------------------------------------------------
-- Brief    RISC-V Decode pipeline stage
--          Breaks down instructions into their specific components,
--          Reads from & Writes into the register file,
--          Generate outputs needed for the Execute stage
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;

library work;
use work.riscv_pkg.all;

entity riscv_decode is
  port (
    -- Entrées provenant de l'étage FETCH
    i_instruction : in std_logic_vector(XLEN-1 downto 0);
    i_pc : in std_logic_vector(XLEN-1 downto 0);

    -- Entrées provenant de l'étage WRITE-BACK
    i_wr_addr : in std_logic_vector(REG_WIDTH-1 downto 0);
    i_wr_data : in std_logic_vector(REG_WIDTH-1 downto 0);
    i_we      : in std_logic;

    -- Entrée provenant de l'étage EXECUTE
    i_flush : in std_logic;

    -- Entrées externes au pipeline
    i_rstn : in std_logic;
    i_clk  : in std_logic;

    -- Sortie
    o_rs1_data : out std_logic_vector(XLEN-1 downto 0);
    o_rs2_data : out std_logic_vector(XLEN-1 downto 0);

    o_shamt : out std_logic_vector(SHAMT_WIDTH-1 downto 0);
    o_arith : out std_logic;
    o_sign  : out std_logic;

    o_jump   : out std_logic;
    o_branch : out std_logic;
    o_pc     : out std_logic_vector(XLEN-1 downto 0);
    o_imm    : out std_logic_vector(XLEN-1 downto 0));
end entity riscv_decode;


architecture beh of riscv_decode is
  -- Signaux internes Predecode
  -- opcode funct3 funct7 rs1 rs2
  -- jump
  -- branch
  -- imm

  -- Signaux internes Decode
  -- alu_opcode
  -- shamt
  -- arith
  -- sign
begin

  -- Predecode


  -- Instanciation du Register File


  -- Decode


  -- Écrire le registre ID/EX



  -- DEBUG:
  o_rs1_data <= (others => '1');
  o_rs2_data <= (others => '1');

  o_shamt <= (others => '1');
  o_arith <= '1';
  o_sign  <= '1';

  o_jump   <= '1';
  o_branch <= '1';
  o_pc     <= (others => '1');
  o_imm    <= (others => '1');

  -- Références:
  -- Écrire le registre pointé
--  write_reg_file:
--  process (i_clk) is
--  begin
--
--    if rising_edge(i_clk) then
--      if i_rstn = '1' then
--        if reg_file_wr_en = '1' then
--          reg_file(to_integer(unsigned(i_addr_w))) <= i_data_w;
--        else
--          reg_file <= reg_file;
--        end if;
--      else
--        reg_file <= (others => (others => '0'));
--      end if;
--    end if;
--  end process write_reg_file;

  -- Transférer la valeur écrite vers un tampon
--  transfer_write_buffers:
--  process (i_clk) is
--  begin
--    if rising_edge(i_clk) then
--      if i_rstn = '1' then
--        write_buffer <= i_data_w;
--      else
--        write_buffer <= (others => '0');
--      end if;
--    end if;
--  end process transfer_write_buffers;
end architecture beh;